Commit 1ff7a6c5 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: rename TSPLL and CGU functions and definitions 



Rename TSPLL and CGU functions, definitions etc. to match the file name
and have consistent naming scheme.

Reviewed-by: default avatarMichal Kubiak <michal.kubiak@intel.com>
Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent be7f0c1f

drivers/net/ethernet/intel/ice/ice_common.c

+14 −14
Original line number Diff line number Diff line
@@ -2301,12 +2301,12 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);

		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);

	} else {

		info->clk_freq = ICE_TIME_REF_FREQ_156_250;

		info->clk_freq = ICE_TSPLL_FREQ_156_250;

		info->clk_src = ICE_CLK_SRC_TCXO;

	}



	if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {

		info->time_ref = (enum ice_time_ref_freq)info->clk_freq;

	if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {

		info->time_ref = (enum ice_tspll_freq)info->clk_freq;

	} else {

		/* Unknown clock frequency, so assume a (probably incorrect)

		 * default to avoid out-of-bounds look ups of frequency
@@ -2314,7 +2314,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		 */

		ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",

			  info->clk_freq);

		info->time_ref = ICE_TIME_REF_FREQ_25_000;

		info->time_ref = ICE_TSPLL_FREQ_25_000;

	}



	ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
@@ -6134,17 +6134,17 @@ u32 ice_get_link_speed(u16 index) 
}



/**

 * ice_read_cgu_reg_e82x - Read a CGU register

 * @hw: pointer to the HW struct

 * ice_read_cgu_reg - Read a CGU register

 * @hw: Pointer to the HW struct

 * @addr: Register address to read

 * @val: storage for register value read

 * @val: Storage for register value read

 *

 * Read the contents of a register of the Clock Generation Unit. Only

 * applicable to E822 devices.

 * applicable to E82X devices.

 *

 * Return: 0 on success, other error codes when failed to read from CGU.

 */

int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)

int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val)

{

	struct ice_sbq_msg_input cgu_msg = {

		.opcode = ice_sbq_msg_rd,
@@ -6166,17 +6166,17 @@ int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 
}



/**

 * ice_write_cgu_reg_e82x - Write a CGU register

 * @hw: pointer to the HW struct

 * ice_write_cgu_reg - Write a CGU register

 * @hw: Pointer to the HW struct

 * @addr: Register address to write

 * @val: value to write into the register

 * @val: Value to write into the register

 *

 * Write the specified value to a register of the Clock Generation Unit. Only

 * applicable to E822 devices.

 * applicable to E82X devices.

 *

 * Return: 0 on success, other error codes when failed to write to CGU.

 */

int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)

int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val)

{

	struct ice_sbq_msg_input cgu_msg = {

		.opcode = ice_sbq_msg_wr,

drivers/net/ethernet/intel/ice/ice_common.h

+18 −18
Original line number Diff line number Diff line
@@ -39,8 +39,8 @@ 
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)

#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)



#define NAC_CGU_DWORD9 0x24

union nac_cgu_dword9 {

#define ICE_CGU_R9 0x24

union ice_cgu_r9 {

	struct {

		u32 time_ref_freq_sel : 3;

		u32 clk_eref1_en : 1;
@@ -62,24 +62,24 @@ union nac_cgu_dword9 { 
	u32 val;

};



#define NAC_CGU_DWORD16_E825C 0x40

union nac_cgu_dword16_e825c {

#define ICE_CGU_R16 0x40

union ice_cgu_r16 {

	struct {

		u32 synce_remndr : 6;

		u32 synce_phlmt_en : 1;

		u32 misc13 : 17;

		u32 tspll_ck_refclkfreq : 8;

		u32 ck_refclkfreq : 8;

	};

	u32 val;

};



#define NAC_CGU_DWORD19 0x4c

union nac_cgu_dword19 {

#define ICE_CGU_R19 0x4c

union ice_cgu_r19 {

	struct {

		u32 tspll_fbdiv_intgr : 8;

		u32 fbdiv_intgr : 8;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 3;

		u32 tspll_ndivratio : 4;

		u32 ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;
@@ -89,8 +89,8 @@ union nac_cgu_dword19 { 
	u32 val;

};



#define NAC_CGU_DWORD22 0x58

union nac_cgu_dword22 {

#define ICE_CGU_R22 0x58

union ice_cgu_r22 {

	struct {

		u32 fdpll_frac_div_out_nc : 2;

		u32 fdpll_lock_int_for : 1;
@@ -113,8 +113,8 @@ union nac_cgu_dword22 { 
	u32 val;

};



#define NAC_CGU_DWORD23_E825C 0x5C

union nac_cgu_dword23_e825c {

#define ICE_CGU_R23 0x5C

union ice_cgu_r23 {

	struct {

		u32 cgupll_fbdiv_intgr : 10;

		u32 ux56pll_fbdiv_intgr : 10;
@@ -129,10 +129,10 @@ union nac_cgu_dword23_e825c { 
	u32 val;

};



#define NAC_CGU_DWORD24 0x60

union nac_cgu_dword24 {

#define ICE_CGU_R24 0x60

union ice_cgu_r24 {

	struct {

		u32 tspll_fbdiv_frac : 22;

		u32 fbdiv_frac : 22;

		u32 misc20 : 2;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;
@@ -480,6 +480,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);

int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);

bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);

int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val);

int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val);

int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);

int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);

#endif /* _ICE_COMMON_H_ */

drivers/net/ethernet/intel/ice/ice_ptp.c

+1 −1
Original line number Diff line number Diff line
@@ -1636,7 +1636,7 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, 
		int err;



		/* Enable/disable CGU 1PPS output for E825C */

		err = ice_cgu_cfg_pps_out(hw, !!period);

		err = ice_tspll_cfg_pps_out_e825c(hw, !!period);

		if (err)

			return err;

	}

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

+8 −8
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = { 


/* struct ice_time_ref_info_e82x

 *

 * E822 hardware can use different sources as the reference for the PTP

 * E82X hardware can use different sources as the reference for the PTP

 * hardware clock. Each clock has different characteristics such as a slightly

 * different frequency, etc.

 *
@@ -289,8 +289,8 @@ struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = { 
 * reference. See the struct ice_time_ref_info_e82x for information about the

 * meaning of each constant.

 */

const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {

	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */

const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TSPLL_FREQ] = {

	/* ICE_TSPLL_FREQ_25_000 -> 25 MHz */

	{

		/* pll_freq */

		823437500, /* 823.4375 MHz PLL */
@@ -298,7 +298,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
		0x136e44fabULL,

	},



	/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */

	/* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */

	{

		/* pll_freq */

		783360000, /* 783.36 MHz */
@@ -306,7 +306,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
		0x146cc2177ULL,

	},



	/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */

	/* ICE_TSPLL_FREQ_125_000 -> 125 MHz */

	{

		/* pll_freq */

		796875000, /* 796.875 MHz */
@@ -314,7 +314,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
		0x141414141ULL,

	},



	/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */

	/* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */

	{

		/* pll_freq */

		816000000, /* 816 MHz */
@@ -322,7 +322,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
		0x139b9b9baULL,

	},



	/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */

	/* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */

	{

		/* pll_freq */

		830078125, /* 830.78125 MHz */
@@ -330,7 +330,7 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
		0x134679aceULL,

	},



	/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */

	/* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */

	{

		/* pll_freq */

		783360000, /* 783.36 MHz */

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+2 −2
Original line number Diff line number Diff line
@@ -2126,7 +2126,7 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 
static int ice_ptp_init_phc_e825(struct ice_hw *hw)

{

	/* Initialize the Clock Generation Unit */

	return ice_init_cgu_e82x(hw);

	return ice_tspll_init(hw);

}



/**
@@ -2799,7 +2799,7 @@ static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 
	wr32(hw, PF_SB_REM_DEV_CTL, val);



	/* Initialize the Clock Generation Unit */

	err = ice_init_cgu_e82x(hw);

	err = ice_tspll_init(hw);

	if (err)

		return err;