Commit 1ffe76d5 authored by Shiji Yang's avatar Shiji Yang Committed by Kalle Valo
Browse files

wifi: rt2x00: improve MT7620 register initialization 



1. Do not hard reset the BBP. We can use soft reset instead. This
   change has some help to the calibration failure issue.
2. Enable falling back to legacy rate from the HT/RTS rate by
   setting the HT_FBK_TO_LEGACY register.
3. Implement MCS rate specific maximum PSDU size. It can improve
   the transmission quality under the low RSSI condition.
4. Set BBP_84 register value to 0x19. This is used for extension
   channel overlapping IOT.

Signed-off-by: default avatarShiji Yang <yangshiji66@outlook.com>
Acked-by: default avatarStanislaw Gruszka <stf_xl@wp.pl>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/TYAP286MB031553CCD4B7A3B89C85935DBCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
parent 0057680e

drivers/net/wireless/ralink/rt2x00/rt2800.h

+18 −0
Original line number Diff line number Diff line
@@ -870,6 +870,18 @@ 
#define LED_CFG_Y_LED_MODE		FIELD32(0x30000000)

#define LED_CFG_LED_POLAR		FIELD32(0x40000000)



/*

 * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7

 * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15

 * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7

 * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15

 * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes

 */

#define AMPDU_MAX_LEN_20M1S		0x1030

#define AMPDU_MAX_LEN_20M2S		0x1034

#define AMPDU_MAX_LEN_40M1S		0x1038

#define AMPDU_MAX_LEN_40M2S		0x103C



/*

 * AMPDU_BA_WINSIZE: Force BlockAck window size

 * FORCE_WINSIZE_ENABLE:
@@ -1545,6 +1557,12 @@ 
 */

#define EXP_ACK_TIME			0x1380



/*

 * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate

 * Not available for legacy SoCs

 */

#define HT_FBK_TO_LEGACY		0x1384



/* TX_PWR_CFG_5 */

#define TX_PWR_CFG_5			0x1384

#define TX_PWR_CFG_5_MCS16_CH0		FIELD32(0x0000000f)

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

+24 −0
Original line number Diff line number Diff line
@@ -5851,6 +5851,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;

	u32 reg;

	u16 eeprom;

	u8 bbp;

	unsigned int i;

	int ret;
@@ -5860,6 +5861,19 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	if (ret)

		return ret;



	if (rt2x00_rt(rt2x00dev, RT6352)) {

		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);



		bbp = rt2800_bbp_read(rt2x00dev, 21);

		bbp |= 0x01;

		rt2800_bbp_write(rt2x00dev, 21, bbp);

		bbp = rt2800_bbp_read(rt2x00dev, 21);

		bbp &= (~0x01);

		rt2800_bbp_write(rt2x00dev, 21, bbp);



		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);

	}



	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);

	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
@@ -6013,6 +6027,14 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);

		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);

		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);



		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);

		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);

		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);

		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);



		rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);



	} else {

		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);

		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -7231,6 +7253,8 @@ static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 
	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);



	rt2800_bbp4_mac_if_ctrl(rt2x00dev);



	rt2800_bbp_write(rt2x00dev, 84, 0x19);

}



static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)

drivers/net/wireless/ralink/rt2x00/rt2800mmio.c

+3 −0
Original line number Diff line number Diff line
@@ -760,6 +760,9 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev) 


	rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);



	if (rt2x00_rt(rt2x00dev, RT6352))

		return 0;



	reg = 0;

	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);

	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);