Commit 2009e808 authored by Akshata Jahagirdar's avatar Akshata Jahagirdar Committed by Matt Roper
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drm/xe/xe2: Introduce performance changes



Add Compression Performance Improvement Changes in Xe2

v2: Rebase

v3: Rebase, updated as per latest changes on bspec,
    Removed unnecessary default actions (Matt)
    formatting nits (Tejas)

v4: Formatting nits, removed default set action for bit 14 (Matt)

Bspec: 72161
Signed-off-by: default avatarAkshata Jahagirdar <akshata.jahagirdar@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com
parent 4f04d07c
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+3 −0
Original line number Diff line number Diff line
@@ -367,6 +367,9 @@
#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
#define   XEHP_LNESPARE				REG_BIT(19)

#define L3SQCREG2				XE_REG_MCR(0xb104)
#define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)

#define L3SQCREG3				XE_REG_MCR(0xb108)
#define   COMPPWOVERFETCHEN			REG_BIT(28)

+5 −0
Original line number Diff line number Diff line
@@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
	},
	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
	  XE_RTP_ACTIONS(SET(L3SQCREG2,
			     COMPMEMRD256BOVRFETCHEN))
	},
	{}
};