Commit 20371ba1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Another week, another set of GPU fixes. amdgpu and vmwgfx leading the
  charge, then i915 and xe changes along with v3d and some other bits.
  The TTM revert is due to some stuttering graphical apps probably due
  to longer stalls while prefaulting.

  Seems pretty much where I'd expect things,

  ttm:
   - revert prefault change, caused stutters

  aperture:
   - handle non-VGA devices bettter

  amdgpu:
   - SWSMU gaming stability fix
   - SMU 13.0.7 fix
   - SWSMU documentation alignment fix
   - SMU 14.0.x fixes
   - GC 12.x fix
   - Display fix
   - IP discovery fix
   - SMU 13.0.6 fix

  i915:
   - Fix #11195: The external display connect via USB type-C dock stays
     blank after re-connect the dock
   - Make DSI backlight work for 2G version of Lenovo Yoga Tab 3 X90F
   - Move ARL GuC firmware to correct version

  xe:
   - Invalidate media_gt TLBs
   - Fix HWMON i1 power setup write command

  vmwgfx:
   - prevent unmapping active read buffers
   - fix prime with external buffers
   - disable coherent dumb buffers without 3d

  v3d:
   - disable preemption while updating GPU stats"

* tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/hwmon: Fix WRITE_I1 param from u32 to u16
  drm/v3d: Disable preemption while updating GPU stats
  drm/amd/pm: Drop unsupported features on smu v14_0_2
  drm/amd/pm: Add support for new P2S table revision
  drm/amdgpu: support for gc_info table v1.3
  drm/amd/display: avoid using null object of framebuffer
  drm/amdgpu/gfx12: set UNORD_DISPATCH in compute MQDs
  drm/amd/pm: update message interface for smu v14.0.2/3
  drm/amdgpu/swsmu: always force a state reprogram on init
  drm/amdgpu/smu13.0.7: print index for profiles
  drm/amdgpu: align pp_power_profile_mode with kernel docs
  drm/i915/dp_mst: Fix MST state after a sink reset
  drm/xe: Invalidate media_gt TLBs
  drm/i915: ARL requires a newer GSC firmware
  drm/i915/dsi: Make Lenovo Yoga Tab 3 X90F DMI match less strict
  video/aperture: optionally match the device in sysfb_disable()
  drm/vmwgfx: Disable coherent dumb buffers without 3d
  drm/vmwgfx: Fix prime with external buffers
  drm/vmwgfx: Prevent unmapping active read buffers
  Revert "drm/ttm: increase ttm pre-fault value to PMD size"
parents 1b5fe536 27f5b729
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+13 −6
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@ static struct platform_device *pd;
static DEFINE_MUTEX(disable_lock);
static bool disabled;

static struct device *sysfb_parent_dev(const struct screen_info *si);

static bool sysfb_unregister(void)
{
	if (IS_ERR_OR_NULL(pd))
@@ -52,6 +54,7 @@ static bool sysfb_unregister(void)

/**
 * sysfb_disable() - disable the Generic System Framebuffers support
 * @dev:	the device to check if non-NULL
 *
 * This disables the registration of system framebuffer devices that match the
 * generic drivers that make use of the system framebuffer set up by firmware.
@@ -61,17 +64,21 @@ static bool sysfb_unregister(void)
 * Context: The function can sleep. A @disable_lock mutex is acquired to serialize
 *          against sysfb_init(), that registers a system framebuffer device.
 */
void sysfb_disable(void)
void sysfb_disable(struct device *dev)
{
	struct screen_info *si = &screen_info;

	mutex_lock(&disable_lock);
	if (!dev || dev == sysfb_parent_dev(si)) {
		sysfb_unregister();
		disabled = true;
	}
	mutex_unlock(&disable_lock);
}
EXPORT_SYMBOL_GPL(sysfb_disable);

#if defined(CONFIG_PCI)
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
{
	/*
	 * TODO: Try to integrate this code into the PCI subsystem
@@ -87,13 +94,13 @@ static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
	return true;
}
#else
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
{
	return false;
}
#endif

static __init struct device *sysfb_parent_dev(const struct screen_info *si)
static struct device *sysfb_parent_dev(const struct screen_info *si)
{
	struct pci_dev *pdev;

+11 −0
Original line number Diff line number Diff line
@@ -1500,6 +1500,7 @@ union gc_info {
	struct gc_info_v1_0 v1;
	struct gc_info_v1_1 v1_1;
	struct gc_info_v1_2 v1_2;
	struct gc_info_v1_3 v1_3;
	struct gc_info_v2_0 v2;
	struct gc_info_v2_1 v2_1;
};
@@ -1558,6 +1559,16 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
			adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
			adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
		}
		if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
			adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
			adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
			adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
			adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
			adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
			adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
			adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
			adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
		}
		break;
	case 2:
		adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
+6 −0
Original line number Diff line number Diff line
@@ -240,6 +240,12 @@ struct amdgpu_gfx_config {
	uint32_t gc_tcp_size_per_cu;
	uint32_t gc_num_cu_per_sqc;
	uint32_t gc_tcc_size;
	uint32_t gc_tcp_cache_line_size;
	uint32_t gc_instruction_cache_size_per_sqc;
	uint32_t gc_instruction_cache_line_size;
	uint32_t gc_scalar_data_cache_size_per_sqc;
	uint32_t gc_scalar_data_cache_line_size;
	uint32_t gc_tcc_cache_line_size;
};

struct amdgpu_cu_info {
+1 −1
Original line number Diff line number Diff line
@@ -3005,7 +3005,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
			    (order_base_2(prop->queue_size / 4) - 1));
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
	m->cp_hqd_pq_control |=
			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);

	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
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