Commit 205bd156 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2026-01-23' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Changes for v6.20

GPU:
- Document a612/RGMU dt bindings
- UBWC 6.0 support (for A840 / Kaanapali)
- a225 support
- Fixes

DPU:
- Switched to use virtual planes by default
- Fixed DSI CMD panels on DPU 3.x
- Rewrote format handling to remove intermediate representation
- Fixed watchdog on DPU 8.x+
- Fixed TE / Vsync source setting on DPU 8.x+
- Added 3D_Mux on SC7280
- Kaanapali platform support
- Fixed UBWC register programming
- Made RM reserve DSPP-enabled mixers for CRTCs with LMs.
- Gamma correction support

DP:
- Enabled support for eDP 1.4+ link rate tables
- Fixed MDSS1 DP indices on SA8775P, making them to work
- Fixed msm_dp_ctrl_config_msa() to work with LLVM 20

DSI:
- Documented QCS8300 as compatible with SA8775P
- Kaanapali platform support

DSI PHY:
- switched to divider_determine_rate()

MDP5:
- Dropped support for MSM8998, SDM660 and SDM630 (switched over
  to DPU)

MDSS:
- Kaanapali platform support
- Fixed UBWC register programming

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV03Sbeca93A+gGh-TKpzFYVabbkWVgPCCicG0_NQG+5Y2A@mail.gmail.com
parents 6704d98a 50c4a49f

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+7 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ properties: 
      - items:

          - enum:

              - qcom,apq8064-dsi-ctrl

              - qcom,kaanapali-dsi-ctrl

              - qcom,msm8226-dsi-ctrl

              - qcom,msm8916-dsi-ctrl

              - qcom,msm8953-dsi-ctrl
@@ -45,6 +46,11 @@ properties: 
              - qcom,sm8650-dsi-ctrl

              - qcom,sm8750-dsi-ctrl

          - const: qcom,mdss-dsi-ctrl

      - items:

          - enum:

              - qcom,qcs8300-dsi-ctrl

          - const: qcom,sa8775p-dsi-ctrl

          - const: qcom,mdss-dsi-ctrl

      - enum:

          - qcom,dsi-ctrl-6g-qcm2290

          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
@@ -369,6 +375,7 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,kaanapali-dsi-ctrl

              - qcom,sm8750-dsi-ctrl

    then:

      properties:

Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml

+19 −12
Original line number Diff line number Diff line
@@ -14,9 +14,12 @@ allOf: 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - qcom,dsi-phy-7nm

              - qcom,dsi-phy-7nm-8150

              - qcom,kaanapali-dsi-phy-3nm

              - qcom,sa8775p-dsi-phy-5nm

              - qcom,sar2130p-dsi-phy-5nm

              - qcom,sc7280-dsi-phy-7nm
@@ -26,6 +29,10 @@ properties: 
              - qcom,sm8550-dsi-phy-4nm

              - qcom,sm8650-dsi-phy-4nm

              - qcom,sm8750-dsi-phy-3nm

      - items:

          - enum:

              - qcom,qcs8300-dsi-phy-5nm

          - const: qcom,sa8775p-dsi-phy-5nm



  reg:

    items:

Documentation/devicetree/bindings/display/msm/gpu.yaml

+62 −23
Original line number Diff line number Diff line
@@ -45,11 +45,11 @@ properties: 
          - const: amd,imageon



  clocks:

    minItems: 2

    minItems: 1

    maxItems: 7



  clock-names:

    minItems: 2

    minItems: 1

    maxItems: 7



  reg:
@@ -378,23 +378,62 @@ allOf: 
            - const: xo

              description: GPUCC clocksource clock



      required:

        - clocks

        - clock-names



  - if:

      properties:

        compatible:

          contains:

            const: qcom,adreno-612.0

    then:

      properties:

        clocks:

          items:

            - description: GPU Core clock



        clock-names:

          items:

            - const: core



        reg:

          minItems: 3

          maxItems: 3



        reg-names:

          minItems: 1

          items:

            - const: kgsl_3d0_reg_memory

            - const: cx_mem

            - const: cx_dbgc



      required:

        - clocks

        - clock-names

    else:

      if:



  - if:

      properties:

        compatible:

          contains:

              oneOf:

                - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'

                - pattern: '^qcom,adreno-[0-9a-f]{8}$'

            enum:

              - qcom,adreno-615.0

              - qcom,adreno-618.0

              - qcom,adreno-619.0

              - qcom,adreno-621.0

              - qcom,adreno-623.0

              - qcom,adreno-630.2

              - qcom,adreno-635.0

              - qcom,adreno-640.1

              - qcom,adreno-650.2

              - qcom,adreno-660.1

              - qcom,adreno-663.0

              - qcom,adreno-680.1

              - qcom,adreno-690.0

              - qcom,adreno-730.1

              - qcom,adreno-43030c00

              - qcom,adreno-43050a01

              - qcom,adreno-43050c01

              - qcom,adreno-43051401



    then: # Starting with A6xx, the clocks are usually defined in the GMU node

      properties:

Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml

0 → 100644
+126 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

%YAML 1.2

---



$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: RGMU attached to certain Adreno GPUs



maintainers:

  - Rob Clark <robin.clark@oss.qualcomm.com>



description:

  RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that

  belong to Adreno A6xx family. It is a small state machine that helps to

  toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save

  power.



properties:

  compatible:

    items:

      - const: qcom,adreno-rgmu-612.0

      - const: qcom,adreno-rgmu



  reg:

    items:

      - description: Core RGMU registers



  clocks:

    items:

      - description: GMU clock

      - description: GPU CX clock

      - description: GPU AXI clock

      - description: GPU MEMNOC clock

      - description: GPU SMMU vote clock



  clock-names:

    items:

      - const: gmu

      - const: cxo

      - const: axi

      - const: memnoc

      - const: smmu_vote



  power-domains:

    items:

      - description: CX GDSC power domain

      - description: GX GDSC power domain



  power-domain-names:

    items:

      - const: cx

      - const: gx



  interrupts:

    items:

      - description: GMU OOB interrupt

      - description: GMU interrupt



  interrupt-names:

    items:

      - const: oob

      - const: gmu



  operating-points-v2: true

  opp-table:

    type: object



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - power-domains

  - power-domain-names

  - interrupts

  - interrupt-names

  - operating-points-v2



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,qcs615-gpucc.h>

    #include <dt-bindings/clock/qcom,qcs615-gcc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    gmu@506a000 {

        compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";



        reg = <0x05000000 0x90000>;



        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

                 <&gpucc GPU_CC_CXO_CLK>,

                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

        clock-names = "gmu",

                      "cxo",

                      "axi",

                      "memnoc",

                      "smmu_vote";



        power-domains = <&gpucc CX_GDSC>,

                        <&gpucc GX_GDSC>;

        power-domain-names = "cx",

                             "gx";



        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "oob",

                          "gmu";



        operating-points-v2 = <&gmu_opp_table>;



        gmu_opp_table: opp-table {

            compatible = "operating-points-v2";



            opp-200000000 {

                opp-hz = /bits/ 64 <200000000>;

                required-opps = <&rpmhpd_opp_low_svs>;

            };

        };

    };

Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml

0 → 100644
+297 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Kaanapali Display MDSS



maintainers:

  - Yongxing Mou <yongxing.mou@oss.qualcomm.com>

  - Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>



description:

  Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks

  like DPU display controller, DSI and DP interfaces etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,kaanapali-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core

      - description: Display AHB SWI



  iommus:

    maxItems: 1



  interconnects:

    items:

      - description: Interconnect path from mdp0 port to the data bus

      - description: Interconnect path from CPU to the reg bus



  interconnect-names:

    items:

      - const: mdp0-mem

      - const: cpu-cfg



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,kaanapali-dpu



  "^dsi@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,kaanapali-dsi-ctrl



  "^phy@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,kaanapali-dsi-phy-3nm



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy-qcom-qmp.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-subsystem@9800000 {

        compatible = "qcom,kaanapali-mdss";

        reg = <0x09800000 0x1000>;

        reg-names = "mdss";



        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;



        clocks = <&disp_cc_mdss_ahb_clk>,

                 <&gcc_disp_hf_axi_clk>,

                 <&disp_cc_mdss_mdp_clk>,

                 <&disp_cc_mdss_ahb_swi_clk>;

        resets = <&disp_cc_mdss_core_bcr>;



        power-domains = <&mdss_gdsc>;



        iommus = <&apps_smmu 0x800 0x2>;



        interrupt-controller;

        #interrupt-cells = <1>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        display-controller@9801000 {

            compatible = "qcom,kaanapali-dpu";

            reg = <0x09801000 0x1c8000>,

                  <0x09b16000 0x3000>;

            reg-names = "mdp",

                        "vbif";



            interrupts-extended = <&mdss 0>;



            clocks = <&gcc_disp_hf_axi_clk>,

                     <&disp_cc_mdss_ahb_clk>,

                     <&disp_cc_mdss_mdp_lut_clk>,

                     <&disp_cc_mdss_mdp_clk>,

                     <&disp_cc_mdss_vsync_clk>;

            clock-names = "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";



            assigned-clocks = <&disp_cc_mdss_vsync_clk>;

            assigned-clock-rates = <19200000>;



            operating-points-v2 = <&mdp_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    dpu_intf1_out: endpoint {

                        remote-endpoint = <&mdss_dsi0_in>;

                    };

                };



                port@1 {

                    reg = <1>;



                    dpu_intf2_out: endpoint {

                        remote-endpoint = <&mdss_dsi1_in>;

                    };

                };

            };



            mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-156000000 {

                    opp-hz = /bits/ 64 <156000000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-207000000 {

                    opp-hz = /bits/ 64 <207000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-337000000 {

                    opp-hz = /bits/ 64 <337000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-417000000 {

                    opp-hz = /bits/ 64 <417000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-532000000 {

                    opp-hz = /bits/ 64 <532000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };



                opp-600000000 {

                    opp-hz = /bits/ 64 <600000000>;

                    required-opps = <&rpmhpd_opp_nom_l1>;

                };



                opp-650000000 {

                    opp-hz = /bits/ 64 <650000000>;

                    required-opps = <&rpmhpd_opp_turbo>;

                };

            };

        };



        dsi@9ac0000 {

            compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";

            reg = <0x09ac0000 0x1000>;

            reg-names = "dsi_ctrl";



            interrupts-extended = <&mdss 4>;



            clocks = <&disp_cc_mdss_byte0_clk>,

                     <&disp_cc_mdss_byte0_intf_clk>,

                     <&disp_cc_mdss_pclk0_clk>,

                     <&disp_cc_mdss_esc0_clk>,

                     <&disp_cc_mdss_ahb_clk>,

                     <&gcc_disp_hf_axi_clk>,

                     <&mdss_dsi0_phy 1>,

                     <&mdss_dsi0_phy 0>,

                     <&disp_cc_esync0_clk>,

                     <&disp_cc_osc_clk>,

                     <&disp_cc_mdss_byte0_clk_src>,

                     <&disp_cc_mdss_pclk0_clk_src>;

            clock-names = "byte",

                          "byte_intf",

                          "pixel",

                          "core",

                          "iface",

                          "bus",

                          "dsi_pll_pixel",

                          "dsi_pll_byte",

                          "esync",

                          "osc",

                          "byte_src",

                          "pixel_src";



            operating-points-v2 = <&mdss_dsi_opp_table>;



            power-domains = <&rpmhpd RPMHPD_MMCX>;



            phys = <&mdss_dsi0_phy>;

            phy-names = "dsi";



            #address-cells = <1>;

            #size-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    mdss_dsi0_in: endpoint {

                        remote-endpoint = <&dpu_intf1_out>;

                    };

                };



                port@1 {

                    reg = <1>;



                    mdss_dsi0_out: endpoint {

                        remote-endpoint = <&panel0_in>;

                        data-lanes = <0 1 2 3>;

                    };

                };

            };



            mdss_dsi_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-187500000 {

                    opp-hz = /bits/ 64 <187500000>;

                    required-opps = <&rpmhpd_opp_low_svs_d1>;

                };



                opp-250000000 {

                    opp-hz = /bits/ 64 <250000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-312500000 {

                    opp-hz = /bits/ 64 <312500000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-358000000 {

                    opp-hz = /bits/ 64 <358000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };

            };

        };



        mdss_dsi0_phy: phy@9ac1000 {

            compatible = "qcom,kaanapali-dsi-phy-3nm";

            reg = <0x09ac1000 0x1cc>,

                  <0x09ac1200 0x80>,

                  <0x09ac1500 0x400>;

            reg-names = "dsi_phy",

                        "dsi_phy_lane",

                        "dsi_pll";



            clocks = <&disp_cc_mdss_ahb_clk>,

                     <&rpmhcc RPMH_CXO_CLK>;

            clock-names = "iface",

                          "ref";



            #clock-cells = <1>;

            #phy-cells = <0>;

        };

    };