Commit 20611193 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dwc' 

- Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training more
  robust; this will not affect the intended link width if all lanes are
  functional (Wenbin Yao)

* pci/controller/dwc:
  PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to one lane
parents 00c78a3c af3c6eac

drivers/pci/controller/dwc/pcie-designware.c

+1 −4
Original line number Diff line number Diff line
@@ -797,22 +797,19 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 
	/* Set link width speed control register */

	lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);

	lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;

	lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;

	switch (num_lanes) {

	case 1:

		plc |= PORT_LINK_MODE_1_LANES;

		lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;

		break;

	case 2:

		plc |= PORT_LINK_MODE_2_LANES;

		lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;

		break;

	case 4:

		plc |= PORT_LINK_MODE_4_LANES;

		lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;

		break;

	case 8:

		plc |= PORT_LINK_MODE_8_LANES;

		lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;

		break;

	default:

		dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);