Unverified Commit 206994e3 authored by Frank Wunderlich's avatar Frank Wunderlich Committed by AngeloGioacchino Del Regno
Browse files
parent 69b2d44b
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+20 −1
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ watchdog: watchdog@1001c000 {
			#reset-cells = <1>;
		};

		clock-controller@1001e000 {
		apmixedsys: clock-controller@1001e000 {
			compatible = "mediatek,mt7988-apmixedsys";
			reg = <0 0x1001e000 0 0x1000>;
			#clock-cells = <1>;
@@ -290,6 +290,25 @@ usb@11200000 {
			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt7988-mmc";
			reg = <0 0x11230000 0 0x1000>,
			      <0 0x11D60000 0 0x1000>;
			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_MSDC400>,
				 <&infracfg CLK_INFRA_MSDC2_HCK>,
				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		clock-controller@11f40000 {
			compatible = "mediatek,mt7988-xfi-pll";
			reg = <0 0x11f40000 0 0x1000>;