Commit 2091ac69 authored by Sebastian Andrzej Siewior's avatar Sebastian Andrzej Siewior Committed by Alex Deucher
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drm/amd/display: Move the memory allocation out of dcn20_validate_bandwidth_fp(). 



dcn20_validate_bandwidth_fp() is invoked while FPU access has been
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
It is not possible to allocate memory with disabled preemption even with
GFP_ATOMIC on PREEMPT_RT.

Move the memory allocation before FPU access is enabled.
To preserve previous "clean" state of "pipes" add a memset() before the
second invocation of dcn20_validate_bandwidth_internal() where the
variable is used.

Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 941e8036

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+9 −1
Original line number Diff line number Diff line
@@ -2141,9 +2141,17 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
		bool fast_validate)

{

	bool voltage_supported;

	display_e2e_pipe_params_st *pipes;



	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

	if (!pipes)

		return false;



	DC_FP_START();

	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);

	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);

	DC_FP_END();



	kfree(pipes);

	return voltage_supported;

}

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+7 −9
Original line number Diff line number Diff line
@@ -1925,7 +1925,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st 
}



static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,

		bool fast_validate)

		bool fast_validate, display_e2e_pipe_params_st *pipes)

{

	bool out = false;
@@ -1934,7 +1934,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);

	DC_LOGGER_INIT(dc->ctx->logger);



	BW_VAL_TRACE_COUNT();
@@ -1969,16 +1968,14 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	out = false;



validate_out:

	kfree(pipes);



	BW_VAL_TRACE_FINISH();



	return out;

}



bool dcn20_validate_bandwidth_fp(struct dc *dc,

				 struct dc_state *context,

				 bool fast_validate)

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

				 bool fast_validate, display_e2e_pipe_params_st *pipes)

{

	bool voltage_supported = false;

	bool full_pstate_supported = false;
@@ -1997,11 +1994,11 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, 
	ASSERT(context != dc->current_state);



	if (fast_validate) {

		return dcn20_validate_bandwidth_internal(dc, context, true);

		return dcn20_validate_bandwidth_internal(dc, context, true, pipes);

	}



	// Best case, we support full UCLK switch latency

	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);

	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);

	full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;



	if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
@@ -2013,7 +2010,8 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, 
	// Fallback: Try to only support G6 temperature read latency

	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;



	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);

	memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));

	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);

	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;



	if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

+2 −3
Original line number Diff line number Diff line
@@ -61,9 +61,8 @@ void dcn20_update_bounding_box(struct dc *dc, 
			       unsigned int num_states);

void dcn20_patch_bounding_box(struct dc *dc,

			      struct _vcs_dpi_soc_bounding_box_st *bb);

bool dcn20_validate_bandwidth_fp(struct dc *dc,

				 struct dc_state *context,

				 bool fast_validate);

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

				 bool fast_validate, display_e2e_pipe_params_st *pipes);

void dcn20_fpu_set_wm_ranges(int i,

			     struct pp_smu_wm_range_sets *ranges,

			     struct _vcs_dpi_soc_bounding_box_st *loaded_bb);