Commit 209efec1 authored by Wolfram Sang's avatar Wolfram Sang Committed by Vinod Koul
Browse files

dt-bindings: dma: rz-dmac: Document RZ/A1H SoC 



Document the Renesas RZ/A1H DMAC block. This one does not have clocks,
resets and power domains. Update the bindings accordingly. Introduce a
generic name in the header to make future additions easier.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20241007110200.43166-7-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 6e9c5c8e

Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

+20 −9
Original line number Diff line number Diff line
@@ -4,18 +4,16 @@ 
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller

title: Renesas RZ DMA Controller



maintainers:

  - Biju Das <biju.das.jz@bp.renesas.com>



allOf:

  - $ref: dma-controller.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r7s72100-dmac # RZ/A1H

          - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five

          - renesas,r9a07g044-dmac # RZ/G2{L,LC}

          - renesas,r9a07g054-dmac # RZ/V2L
@@ -93,10 +91,23 @@ required: 
  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - '#dma-cells'

  - dma-channels



allOf:

  - $ref: dma-controller.yaml#



  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - renesas,r7s72100-dmac

    then:

      required:

        - clocks

        - clock-names

        - power-domains

        - resets

        - reset-names