Commit 20c34e5c authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Fix core reset sequence for JPEG4_0_3 



For cores 1 through 7 repair the core reset sequence by
adjusting offsets to access the expected registers.

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a91d91b6

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

+5 −9
Original line number Diff line number Diff line
@@ -1104,24 +1104,20 @@ static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring) 
	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,

			    reg_offset, 0x1F);

	SOC15_WAIT_ON_RREG(JPEG, jpeg_inst,

	SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst,

				  regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS,

			   0x1F, 0x1F);

				  reg_offset, 0x1F, 0x1F);

	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regUVD_JMI0_JPEG_LMI_DROP,

			    reg_offset, 0x1F);

	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regJPEG_CORE_RST_CTRL,

			    reg_offset, 1 << ring->pipe);

	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe);

	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,

			    reg_offset, 0x00);

	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regUVD_JMI0_JPEG_LMI_DROP,

			    reg_offset, 0x00);

	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,

			    regJPEG_CORE_RST_CTRL,

			    reg_offset, 0x00);

	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00);

}



static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)