Commit 20f33275 authored by Antonino Maniscalco's avatar Antonino Maniscalco Committed by Rob Clark
Browse files

drm/msm/a6xx: Enable preemption for tested a7xx targets 



Initialize with 4 rings to enable preemption.

Add the "preemption_enabled" module parameter to override this.

Tested-by: default avatarRob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618029/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 7788d320

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+8 −4
Original line number Diff line number Diff line
@@ -1337,7 +1337,8 @@ static const struct adreno_info a7xx_gpus[] = { 
		.gmem = SZ_2M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |

			  ADRENO_QUIRK_HAS_HW_APRIV,

			  ADRENO_QUIRK_HAS_HW_APRIV |

			  ADRENO_QUIRK_PREEMPTION,

		.init = a6xx_gpu_init,

		.zapfw = "a730_zap.mdt",

		.a6xx = &(const struct a6xx_info) {
@@ -1358,7 +1359,8 @@ static const struct adreno_info a7xx_gpus[] = { 
		.gmem = 3 * SZ_1M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |

			  ADRENO_QUIRK_HAS_HW_APRIV,

			  ADRENO_QUIRK_HAS_HW_APRIV |

			  ADRENO_QUIRK_PREEMPTION,

		.init = a6xx_gpu_init,

		.zapfw = "a740_zap.mdt",

		.a6xx = &(const struct a6xx_info) {
@@ -1380,7 +1382,8 @@ static const struct adreno_info a7xx_gpus[] = { 
		.gmem = 3 * SZ_1M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |

			  ADRENO_QUIRK_HAS_HW_APRIV,

			  ADRENO_QUIRK_HAS_HW_APRIV |

			  ADRENO_QUIRK_PREEMPTION,

		.init = a6xx_gpu_init,

		.a6xx = &(const struct a6xx_info) {

			.hwcg = a740_hwcg,
@@ -1401,7 +1404,8 @@ static const struct adreno_info a7xx_gpus[] = { 
		.gmem = 3 * SZ_1M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |

			  ADRENO_QUIRK_HAS_HW_APRIV,

			  ADRENO_QUIRK_HAS_HW_APRIV |

			  ADRENO_QUIRK_PREEMPTION,

		.init = a6xx_gpu_init,

		.zapfw = "gen70900_zap.mbn",

		.a6xx = &(const struct a6xx_info) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+5 −1
Original line number Diff line number Diff line
@@ -2436,6 +2436,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 
	struct a6xx_gpu *a6xx_gpu;

	struct adreno_gpu *adreno_gpu;

	struct msm_gpu *gpu;

	extern int enable_preemption;

	bool is_a7xx;

	int ret;
@@ -2474,7 +2475,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 
		return ERR_PTR(ret);

	}



	if (is_a7xx)

	if ((enable_preemption == 1) || (enable_preemption == -1 &&

	    (config->info->quirks & ADRENO_QUIRK_PREEMPTION)))

		ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4);

	else if (is_a7xx)

		ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1);

	else if (adreno_has_gmu_wrapper(adreno_gpu))

		ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1);

drivers/gpu/drm/msm/adreno/adreno_device.c

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ bool allow_vram_carveout = false; 
MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");

module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);



int enable_preemption = -1;

MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))");

module_param(enable_preemption, int, 0600);



extern const struct adreno_gpulist a2xx_gpulist;

extern const struct adreno_gpulist a3xx_gpulist;

extern const struct adreno_gpulist a4xx_gpulist;

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ enum adreno_family { 
#define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)

#define ADRENO_QUIRK_HAS_HW_APRIV		BIT(3)

#define ADRENO_QUIRK_HAS_CACHED_COHERENT	BIT(4)

#define ADRENO_QUIRK_PREEMPTION			BIT(5)



/* Helper for formating the chip_id in the way that userspace tools like

 * crashdec expect.

drivers/gpu/drm/msm/msm_submitqueue.c

+5 −1
Original line number Diff line number Diff line
@@ -161,6 +161,8 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 
	struct msm_drm_private *priv = drm->dev_private;

	struct msm_gpu_submitqueue *queue;

	enum drm_sched_priority sched_prio;

	extern int enable_preemption;

	bool preemption_supported;

	unsigned ring_nr;

	int ret;
@@ -170,7 +172,9 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 
	if (!priv->gpu)

		return -ENODEV;



	if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && priv->gpu->nr_rings == 1)

	preemption_supported = priv->gpu->nr_rings == 1 && enable_preemption != 0;



	if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && preemption_supported)

		return -EINVAL;



	ret = msm_gpu_convert_priority(priv->gpu, prio, &ring_nr, &sched_prio);