Commit 216be476 authored by Shiwu Zhang's avatar Shiwu Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: fix the gb_addr_config_fields init value mismatch 



For gfx_v9_4_3 specifically, before regGB_ADDR_CONFIG is overwritten
in gfx hw_init it is read out to popluate the gb_addr_config_fields
in the sw_init stage, which causes mismatch.

Fix it by using the golden value in sw_init as well.

v2: This is a driver-set golden reg and keep as it is (Lijo)

Signed-off-by: default avatarShiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3bc7bc73

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+1 −5
Original line number Diff line number Diff line
@@ -916,8 +916,6 @@ static const struct aca_info gfx_v9_4_3_aca_info = { 


static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)

{

	u32 gb_addr_config;



	adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;

	adev->gfx.ras = &gfx_v9_4_3_ras;
@@ -926,9 +924,7 @@ static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 
	adev->gfx.config.sc_prim_fifo_size_backend = 0x100;

	adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;

	adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;

	gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);



	adev->gfx.config.gb_addr_config = gb_addr_config;

	adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG;



	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<

			REG_GET_FIELD(