Commit 216e4cff authored by Amber Lin's avatar Amber Lin Committed by Alex Deucher
Browse files

drm/amdgpu: Add chain runlists support to GC9.4.2 



Starting from MEC v97, GC 9.4.2 supports chain runlists of XNACK+/XNACK-
processes.

Signed-off-by: default avatarAmber Lin <Amber.Lin@amd.com>
Reviewed-by: default avatarPhilip <Yang&lt;Philip.Yang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c5fc24f1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -2650,6 +2650,9 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 
				!READ_ONCE(adev->barrier_has_auto_waitcnt));

		WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);

		break;

	case IP_VERSION(9, 4, 2):

		gfx_v9_4_2_init_sq(adev);

		break;

	default:

		break;

	}

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

+12 −0
Original line number Diff line number Diff line
@@ -748,6 +748,18 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, 
	}

}



void gfx_v9_4_2_init_sq(struct amdgpu_device *adev)

{

	uint32_t data;



	if (adev->gfx.mec_fw_version >= 98) {

		adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN;

		data = RREG32_SOC15(GC, 0, regSQ_CONFIG1);

		data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);

		WREG32_SOC15(GC, 0, regSQ_CONFIG1, data);

	}

}



void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,

				uint32_t first_vmid,

				uint32_t last_vmid)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, 
				uint32_t first_vmid, uint32_t last_vmid);

void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,

				      uint32_t die_id);

void gfx_v9_4_2_init_sq(struct amdgpu_device *adev);

void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);

int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev);