Commit 21741810 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: add more pipe resource interfaces 



Redesign pipe resource interfaces in resource.h file. The new interface
design addresses the issue with lack of pipe topology encapsulation and
lack of pipe accessors.

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7b0c688d

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+541 −410

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+2 −0
Original line number Diff line number Diff line
@@ -614,6 +614,8 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

	pipe_ctx->top_pipe = NULL;

	pipe_ctx->bottom_pipe = NULL;

	pipe_ctx->prev_odm_pipe = NULL;

	pipe_ctx->next_odm_pipe = NULL;

	pipe_ctx->plane_state = NULL;

}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+16 −6
Original line number Diff line number Diff line
@@ -1948,7 +1948,7 @@ int dcn20_validate_apply_pipe_split_flags( 
			v->ODMCombineEnablePerState[vlevel][pipe_plane];



		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {

			if (resource_get_num_mpc_splits(pipe) == 1) {

			if (resource_get_mpc_slice_count(pipe) == 2) {

				/*If need split for mpc but 2 way split already*/

				if (split[i] == 4)

					split[i] = 2; /* 2 -> 4 MPC */
@@ -1956,7 +1956,7 @@ int dcn20_validate_apply_pipe_split_flags( 
					split[i] = 0; /* 2 -> 2 MPC */

				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

					merge[i] = true; /* 2 -> 1 MPC */

			} else if (resource_get_num_mpc_splits(pipe) == 3) {

			} else if (resource_get_mpc_slice_count(pipe) == 4) {

				/*If need split for mpc but 4 way split already*/

				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)

						|| !pipe->bottom_pipe)) {
@@ -1965,7 +1965,7 @@ int dcn20_validate_apply_pipe_split_flags( 
						pipe->top_pipe->plane_state == pipe->plane_state)

					merge[i] = true; /* 4 -> 1 MPC */

				split[i] = 0;

			} else if (resource_get_num_odm_splits(pipe)) {

			} else if (resource_get_odm_slice_count(pipe) > 1) {

				/* ODM -> MPC transition */

				if (pipe->prev_odm_pipe) {

					split[i] = 0;
@@ -1973,7 +1973,7 @@ int dcn20_validate_apply_pipe_split_flags( 
				}

			}

		} else {

			if (resource_get_num_odm_splits(pipe) == 1) {

			if (resource_get_odm_slice_count(pipe) == 2) {

				/*If need split for odm but 2 way split already*/

				if (split[i] == 4)

					split[i] = 2; /* 2 -> 4 ODM */
@@ -1983,7 +1983,7 @@ int dcn20_validate_apply_pipe_split_flags( 
					ASSERT(0); /* NOT expected yet */

					merge[i] = true; /* exit ODM */

				}

			} else if (resource_get_num_odm_splits(pipe) == 3) {

			} else if (resource_get_odm_slice_count(pipe) == 4) {

				/*If need split for odm but 4 way split already*/

				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)

						|| !pipe->next_odm_pipe)) {
@@ -1993,7 +1993,7 @@ int dcn20_validate_apply_pipe_split_flags( 
					merge[i] = true; /* exit ODM */

				}

				split[i] = 0;

			} else if (resource_get_num_mpc_splits(pipe)) {

			} else if (resource_get_mpc_slice_count(pipe) > 1) {

				/* MPC -> ODM transition */

				ASSERT(0); /* NOT expected yet */

				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
@@ -2211,12 +2211,22 @@ enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_stat 
	return DC_OK;

}



void dcn20_release_pipe(struct dc_state *context,

			struct pipe_ctx *pipe,

			const struct resource_pool *pool)

{

	if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)

		dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

	memset(pipe, 0, sizeof(*pipe));

}



static const struct resource_funcs dcn20_res_pool_funcs = {

	.destroy = dcn20_destroy_resource_pool,

	.link_enc_create = dcn20_link_encoder_create,

	.panel_cntl_create = dcn20_panel_cntl_create,

	.validate_bandwidth = dcn20_validate_bandwidth,

	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,

	.release_pipe = dcn20_release_pipe,

	.add_stream_to_ctx = dcn20_add_stream_to_ctx,

	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,

	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+3 −1
Original line number Diff line number Diff line
@@ -63,7 +63,9 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer( 
		struct dc_state *new_ctx,

		const struct resource_pool *pool,

		const struct pipe_ctx *opp_head_pipe);



void dcn20_release_pipe(struct dc_state *context,

			struct pipe_ctx *pipe,

			const struct resource_pool *pool);

struct stream_encoder *dcn20_stream_encoder_create(

	enum engine_id eng_id,

	struct dc_context *ctx);

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1069,6 +1069,7 @@ static struct resource_funcs dcn201_res_pool_funcs = { 
	.add_dsc_to_stream_resource = NULL,

	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,

	.acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer,

	.release_pipe = dcn20_release_pipe,

	.populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,

	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

	.set_mcif_arb_params = dcn20_set_mcif_arb_params,