Commit 220928e5 authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/hwcap: Add hwcap for FEAT_LSFE 



FEAT_LSFE (Large System Float Extension), providing atomic floating point
memory operations, is optional from v9.5. This feature adds no new
architectural stare and we have no immediate use for it in the kernel so
simply provide a hwcap for it to support discovery by userspace.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 8f5ae30d

Documentation/arch/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -441,6 +441,10 @@ HWCAP3_MTE_FAR 
HWCAP3_MTE_STORE_ONLY

    Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001.



HWCAP3_LSFE

    Functionality implied by ID_AA64ISAR3_EL1.LSFE == 0b0001





4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
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@@ -178,6 +178,7 @@ 
#define __khwcap3_feature(x)		(const_ilog2(HWCAP3_ ## x) + 128)

#define KERNEL_HWCAP_MTE_FAR		__khwcap3_feature(MTE_FAR)

#define KERNEL_HWCAP_MTE_STORE_ONLY	__khwcap3_feature(MTE_STORE_ONLY)

#define KERNEL_HWCAP_LSFE		__khwcap3_feature(LSFE)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -145,5 +145,6 @@ 
 */

#define HWCAP3_MTE_FAR		(1UL << 0)

#define HWCAP3_MTE_STORE_ONLY		(1UL << 1)

#define HWCAP3_LSFE		(1UL << 2)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+2 −0
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@@ -278,6 +278,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 


static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -3252,6 +3253,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),

	HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT),

	HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX),

	HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE),

	HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),

#ifdef CONFIG_ARM64_SVE

	HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),

arch/arm64/kernel/cpuinfo.c

+1 −0
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@@ -162,6 +162,7 @@ static const char *const hwcap_str[] = { 
	[KERNEL_HWCAP_SME_SMOP4]	= "smesmop4",

	[KERNEL_HWCAP_MTE_FAR]		= "mtefar",

	[KERNEL_HWCAP_MTE_STORE_ONLY]	= "mtestoreonly",

	[KERNEL_HWCAP_LSFE]		= "lsfe",

};



#ifdef CONFIG_COMPAT