Commit 220994d6 authored by Maarten Lankhorst's avatar Maarten Lankhorst
Browse files

Merge remote-tracking branch 'drm/drm-next' into drm-misc-next-fixes 



Seems we missed one drm-misc-next pull-request in drm-misc-next-fixes.
This is required to pull in 5d156a9c ("drm/bridge: Pass down
connector to drm bridge detect hook") and update its docs.

Signed-off-by: default avatarMaarten Lankhorst <dev@lankhorst.se>
parents be71ce97 6531a2cf

Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ properties: 
      - const: samsung,atna33xc20

      - items:

          - enum:

              # Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel

              - samsung,atna30dw01

              # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel

              - samsung,atna40yk20

              # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel

Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml

+0 −6
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@@ -58,12 +58,6 @@ properties: 
  power-domains:

    maxItems: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



required:

  - compatible

  - clocks

Documentation/devicetree/bindings/display/sitronix,st7567.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/sitronix,st7567.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sitronix ST7567 Display Controller



maintainers:

  - Javier Martinez Canillas <javierm@redhat.com>



description:

  Sitronix ST7567 is a driver and controller for monochrome

  dot matrix LCD panels.



allOf:

  - $ref: panel/panel-common.yaml#



properties:

  compatible:

    const: sitronix,st7567



  reg:

    maxItems: 1



  width-mm: true

  height-mm: true

  panel-timing: true



required:

  - compatible

  - reg

  - width-mm

  - height-mm

  - panel-timing



additionalProperties: false



examples:

  - |

    i2c {

        #address-cells = <1>;

        #size-cells = <0>;



        display@3f {

            compatible = "sitronix,st7567";

            reg = <0x3f>;

            width-mm = <37>;

            height-mm = <27>;



            panel-timing {

                hactive = <128>;

                vactive = <64>;

                hback-porch = <0>;

                vback-porch = <0>;

                clock-frequency = <0>;

                hfront-porch = <0>;

                hsync-len = <0>;

                vfront-porch = <0>;

                vsync-len = <0>;

            };

          };

     };

Documentation/gpu/drm-uapi.rst

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@@ -447,7 +447,7 @@ hang is usually the most critical one which can result in consequential hangs or 
complete wedging.



Task information

---------------

----------------



The information about which application (if any) was involved in the device

wedging is useful for userspace if they want to notify the user about what
@@ -460,8 +460,8 @@ event string. 


The reliability of this information is driver and hardware specific, and should

be taken with a caution regarding it's precision. To have a big picture of what

really happened, the devcoredump file provides should have much more detailed

information about the device state and about the event.

really happened, the devcoredump file provides much more detailed information

about the device state and about the event.



Consumer prerequisites

----------------------

Documentation/gpu/nova/core/devinit.rst

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.. SPDX-License-Identifier: GPL-2.0



==================================

Device Initialization (devinit)

==================================

The devinit process is complex and subject to change. This document provides a high-level

overview using the Ampere GPU family as an example. The goal is to provide a conceptual

overview of the process to aid in understanding the corresponding kernel code.



Device initialization (devinit) is a crucial sequence of register read/write operations

that occur after a GPU reset. The devinit sequence is essential for properly configuring

the GPU hardware before it can be used.



The devinit engine is an interpreter program that typically runs on the PMU (Power Management

Unit) microcontroller of the GPU. This interpreter executes a "script" of initialization

commands. The devinit engine itself is part of the VBIOS ROM in the same ROM image as the

FWSEC (Firmware Security) image (see fwsec.rst and vbios.rst) and it runs before the

nova-core driver is even loaded. On an Ampere GPU, the devinit ucode is separate from the

FWSEC ucode. It is launched by FWSEC, which runs on the GSP in 'heavy-secure' mode, while

devinit runs on the PMU in 'light-secure' mode.



Key Functions of devinit

------------------------

devinit performs several critical tasks:



1. Programming VRAM memory controller timings

2. Power sequencing

3. Clock and PLL (Phase-Locked Loop) configuration

4. Thermal management



Low-level Firmware Initialization Flow

--------------------------------------

Upon reset, several microcontrollers on the GPU (such as PMU, SEC2, GSP, etc.) run GPU

firmware (gfw) code to set up the GPU and its core parameters. Most of the GPU is

considered unusable until this initialization process completes.



These low-level GPU firmware components are typically:



1. Located in the VBIOS ROM in the same ROM partition (see vbios.rst and fwsec.rst).

2. Executed in sequence on different microcontrollers:



  - The devinit engine typically but not necessarily runs on the PMU.

  - On an Ampere GPU, the FWSEC typically runs on the GSP (GPU System Processor) in

    heavy-secure mode.



Before the driver can proceed with further initialization, it must wait for a signal

indicating that core initialization is complete (known as GFW_BOOT). This signal is

asserted by the FWSEC running on the GSP in heavy-secure mode.



Runtime Considerations

----------------------

It's important to note that the devinit sequence also needs to run during suspend/resume

operations at runtime, not just during initial boot, as it is critical to power management.



Security and Access Control

---------------------------

The initialization process involves careful privilege management. For example, before

accessing certain completion status registers, the driver must check privilege level

masks. Some registers are only accessible after secure firmware (FWSEC) lowers the

privilege level to allow CPU (LS/low-secure) access. This is the case, for example,

when receiving the GFW_BOOT signal.
 
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