Commit 221d6546 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-intel-next-2023-11-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 

drm/i915 feature pull for v6.8:

Features and functionality:
- Major DP MST improvements on bandwidth management, DSC (Imre, Stan, Ville)
- DP panel replay enabling (Animesh, Jouni)
- MTL C20 phy state verification (Mika)
- MTL DP DSC fractional bpp support (Ankit, Vandita, Swati, Imre)
- Audio fastset support (Ville)

Refactoring and cleanups:
- Use dma fence interfaces instead of i915_sw_fence (Jouni)
- Separate gem and display code (Jouni, Juha-Pekka)
- AUX register macro refactoring (Jani)
- Separate display module/device parameters from the rest (Jouni)
- Move display capabilities debugfs under display (Vinod)
- Makefile cleanup (Jani)
- Register cleanups (Ville)
- Enginer iterator cleanups (Tvrtko)
- Move display lock inits under display/ (Jani)
- VLV/CHV DPIO PHY register and interface refactoring (Jani)
- DSI VBT sequence refactoring (Jani, Andy Shevchenko)
- C10/C20 PHY PLL hardware readout and calculation abstractions (Lucas)
- DPLL code cleanups (Ville)
- Cleanup PXP plane protection checks (Jani)

Fixes:
- Replace VLV/CHV DSI GPIO direct access with proper GPIO API usage (Andy Shevchenko)
- Fix VLV/CHV DSI GPIO wrong initial value (Hans de Goede)
- Fix UHBR data, link M/N/TU and PBN values (Imre)
- Fix HDCP state on an enable/disable cycle (Suraj)
- Fix DP MST modeset sequence to be according to spec (Ville)
- Improved atomicity for multi-pipe commits (Ville)
- Update URLs in i915 MAINTAINERS entry and code (Jani)
- Check for VGA converter presence in eDP probe (Ville)
- Fix surface size checks (Ville)
- Fix LNL port/phy assignment (Lucas)
- Reset C10/C20 message bus harder to avoid sporadic failures (Mika)
- Fix bogus VBT HDMI level shift on BDW (Ville)
- Add workaround for LNL underruns when enabling FBC (Vinod)
- DSB refactoring (Animesh)
- DPT refactoring (Juha-Pekka)
- Disable DSC on DP MST on ICL (Imre)
- Fix PSR VSC packet setup timing (Mika)
- Fix LUT rounding and conversions (Ville)

DRM core display changes:
- DP MST fixes, helpers, refactoring to support bandwidth management (Imre)
- DP MST PBN divider value refactoring and fixes (Imre)
- DPCD register definitions (Ankit, Imre)
- Add helper to get DSC bpp precision (Ankit)
- Fix color LUT rounding (Ville)

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v89sl2ao.fsf@intel.com


[sima: Some conflicts in the amdgpu dp mst code]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parents b26ca735 deac4532

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -10645,9 +10645,9 @@ M: Rodrigo Vivi <rodrigo.vivi@intel.com> 
M:	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>

L:	intel-gfx@lists.freedesktop.org

S:	Supported

W:	https://01.org/linuxgraphics/

W:	https://drm.pages.freedesktop.org/intel-docs/

Q:	http://patchwork.freedesktop.org/project/intel-gfx/

B:	https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs

B:	https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html

C:	irc://irc.oftc.net/intel-gfx

T:	git git://anongit.freedesktop.org/drm-intel

F:	Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+4 −3
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ 
#include <drm/drm_atomic_uapi.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_blend.h>

#include <drm/drm_fixed.h>

#include <drm/drm_fourcc.h>

#include <drm/drm_edid.h>

#include <drm/drm_eld.h>
@@ -6910,8 +6911,8 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 
	if (IS_ERR(mst_state))

		return PTR_ERR(mst_state);



	if (!mst_state->pbn_div)

		mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);

	if (!mst_state->pbn_div.full)

		mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));



	if (!state->duplicated) {

		int max_bpc = conn_state->max_requested_bpc;
@@ -6923,7 +6924,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 
								    max_bpc);

		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;

		clock = adjusted_mode->clock;

		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);

		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);

	}



	dm_new_connector_state->vcpi_slots =

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+2 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include <drm/drm_probe_helper.h>

#include <drm/amdgpu_drm.h>

#include <drm/drm_edid.h>

#include <drm/drm_fixed.h>



#include "dm_services.h"

#include "amdgpu.h"
@@ -210,7 +211,7 @@ static void dm_helpers_construct_old_payload( 
			struct drm_dp_mst_atomic_payload *old_payload)

{

	struct drm_dp_mst_atomic_payload *pos;

	int pbn_per_slot = mst_state->pbn_div;

	int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);

	u8 next_payload_vc_start = mgr->next_start_slot;

	u8 payload_vc_start = new_payload->vc_start_slot;

	u8 allocated_time_slots;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+4 −3
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <drm/display/drm_dp_mst_helper.h>

#include <drm/drm_atomic.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_fixed.h>

#include "dm_services.h"

#include "amdgpu.h"

#include "amdgpu_dm.h"
@@ -941,10 +942,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, 
		link_timeslots_used = 0;



		for (i = 0; i < count; i++)

			link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);

			link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));



		fair_pbn_alloc =

			(63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;

			(63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div);



		if (initial_slack[next_index] > fair_pbn_alloc) {

			vars[next_index].pbn += fair_pbn_alloc;
@@ -1642,7 +1643,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( 
	} else {

		/* check if mode could be supported within full_pbn */

		bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;

		pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);

		pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);

		if (pbn > full_pbn)

			return DC_FAIL_BANDWIDTH_VALIDATE;

	}

drivers/gpu/drm/display/drm_dp_helper.c

+161 −0
Original line number Diff line number Diff line
@@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { 
	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },

	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */

	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },

	/* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */

	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },

	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */

	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },

};
@@ -2326,6 +2328,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 
}

EXPORT_SYMBOL(drm_dp_read_desc);



/**

 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment

 * @dsc_dpcd: DSC capabilities from DPCD

 *

 * Returns the bpp precision supported by the DP sink.

 */

u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

{

	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];



	switch (bpp_increment_dpcd) {

	case DP_DSC_BITS_PER_PIXEL_1_16:

		return 16;

	case DP_DSC_BITS_PER_PIXEL_1_8:

		return 8;

	case DP_DSC_BITS_PER_PIXEL_1_4:

		return 4;

	case DP_DSC_BITS_PER_PIXEL_1_2:

		return 2;

	case DP_DSC_BITS_PER_PIXEL_1_1:

		return 1;

	}



	return 0;

}

EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);



/**

 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count

 * supported by the DSC sink.
@@ -3898,3 +3927,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 
EXPORT_SYMBOL(drm_panel_dp_aux_backlight);



#endif



/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */

static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,

				     int symbol_size, bool is_mst)

{

	int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);

	int align = is_mst ? 4 / lane_count : 1;



	return ALIGN(cycles, align);

}



static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,

					 int bpp_x16, int symbol_size, bool is_mst)

{

	int slice_pixels = DIV_ROUND_UP(pixels, slice_count);

	int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,

							  bpp_x16, symbol_size, is_mst);

	int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;



	return slice_count * (slice_data_cycles + slice_eoc_cycles);

}



/**

 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream

 * @lane_count: DP link lane count

 * @hactive: pixel count of the active period in one scanline of the stream

 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set

 * @bpp_x16: bits per pixel in .4 binary fixed point

 * @flags: DRM_DP_OVERHEAD_x flags

 *

 * Calculate the BW allocation overhead of a DP link stream, depending

 * on the link's

 * - @lane_count

 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)

 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)

 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)

 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)

 * as well as the stream's

 * - @hactive timing

 * - @bpp_x16 color depth

 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).

 * Note that this overhead doesn't account for the 8b/10b, 128b/132b

 * channel coding efficiency, for that see

 * @drm_dp_link_bw_channel_coding_efficiency().

 *

 * Returns the overhead as 100% + overhead% in 1ppm units.

 */

int drm_dp_bw_overhead(int lane_count, int hactive,

		       int dsc_slice_count,

		       int bpp_x16, unsigned long flags)

{

	int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;

	bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;

	u32 overhead = 1000000;

	int symbol_cycles;



	/*

	 * DP Standard v2.1 2.6.4.1

	 * SSC downspread and ref clock variation margin:

	 *   5300ppm + 300ppm ~ 0.6%

	 */

	if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)

		overhead += 6000;



	/*

	 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:

	 * FEC symbol insertions for 8b/10b channel coding:

	 * After each 250 data symbols on 2-4 lanes:

	 *   250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ   (256 byte FEC block)

	 * After each 2 x 250 data symbols on 1 lane:

	 *   2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)

	 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:

	 *   256 * 256 bytes + 1 FEC_PM

	 * or

	 *   128 * 512 bytes + 1 FEC_PM

	 * (256 * 6 + 1) / (256 * 250) = 2.4015625 %

	 */

	if (flags & DRM_DP_BW_OVERHEAD_FEC)

		overhead += 24016;



	/*

	 * DP Standard v2.1 2.7.9, 5.9.7

	 * The FEC overhead for UHBR is accounted for in its 96.71% channel

	 * coding efficiency.

	 */

	WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&

		(flags & DRM_DP_BW_OVERHEAD_FEC));



	if (flags & DRM_DP_BW_OVERHEAD_DSC)

		symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,

							      dsc_slice_count,

							      bpp_x16, symbol_size,

							      is_mst);

	else

		symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,

							  bpp_x16, symbol_size,

							  is_mst);



	return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,

					    overhead * 16),

				hactive * bpp_x16);

}

EXPORT_SYMBOL(drm_dp_bw_overhead);



/**

 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency

 * @is_uhbr: Whether the link has a 128b/132b channel coding

 *

 * Return the channel coding efficiency of the given DP link type, which is

 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes

 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead

 * and for 128b/132b any link or PHY level control symbol insertion overhead

 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the

 * corresponding FEC overhead is BW allocation specific, included in the value

 * returned by drm_dp_bw_overhead().

 *

 * Returns the efficiency in the 100%/coding-overhead% ratio in

 * 1ppm units.

 */

int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)

{

	if (is_uhbr)

		return 967100;

	else

		/*

		 * Note that on 8b/10b MST the efficiency is only

		 * 78.75% due to the 1 out of 64 MTPH packet overhead,

		 * not accounted for here.

		 */

		return 800000;

}

EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);