Unverified Commit 2235e494 authored by Stanimir Varbanov's avatar Stanimir Varbanov Committed by Krzysztof Wilczyński
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dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings 



Add bindings for BCM2712 MSI-X interrupt peripheral controller.

Signed-off-by: default avatarStanimir Varbanov <svarbanov@suse.de>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Tested-by: default avatarIvan T. Ivanov <iivanov@suse.de>
Link: https://lore.kernel.org/r/20250224083559.47645-2-svarbanov@suse.de


[kwilczynski: commit log]
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
parent 2df181e1

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom bcm2712 MSI-X Interrupt Peripheral support



maintainers:

  - Stanimir Varbanov <svarbanov@suse.de>



description:

  This interrupt controller is used to provide interrupt vectors to the

  generic interrupt controller (GIC) on bcm2712. It will be used as

  external MSI-X controller for PCIe root complex.



allOf:

  - $ref: /schemas/interrupt-controller/msi-controller.yaml#



properties:

  compatible:

    const: brcm,bcm2712-mip



  reg:

    items:

      - description: Base register address

      - description: PCIe message address



  "#msi-cells":

    const: 0



  brcm,msi-offset:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: Shift the allocated MSI's.



unevaluatedProperties: false



required:

  - compatible

  - reg

  - msi-controller

  - msi-ranges



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    axi {

        #address-cells = <2>;

        #size-cells = <2>;



        msi-controller@1000130000 {

            compatible = "brcm,bcm2712-mip";

            reg = <0x10 0x00130000 0x00 0xc0>,

                  <0xff 0xfffff000 0x00 0x1000>;

            msi-controller;

            #msi-cells = <0>;

            msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;

        };

    };