Commit 22493f22 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk

parents 59636ec8 3c50137a

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

+44 −0
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ properties: 
    enum:

      - samsung,exynosautov920-cmu-top

      - samsung,exynosautov920-cmu-cpucl0

      - samsung,exynosautov920-cmu-cpucl1

      - samsung,exynosautov920-cmu-cpucl2

      - samsung,exynosautov920-cmu-peric0

      - samsung,exynosautov920-cmu-peric1

      - samsung,exynosautov920-cmu-misc
@@ -94,6 +96,48 @@ allOf: 
            - const: cluster

            - const: dbg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-cpucl1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)

            - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: cluster



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-cpucl2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)

            - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: cluster



  - if:

      properties:

        compatible:

include/dt-bindings/clock/samsung,exynosautov920.h

+32 −0
Original line number Diff line number Diff line
@@ -181,6 +181,38 @@ 
#define CLK_DOUT_CPUCL0_DBG_PCLKDBG	14

#define CLK_DOUT_CPUCL0_NOCP		15



/* CMU_CPUCL1 */

#define CLK_FOUT_CPUCL1_PLL		1



#define CLK_MOUT_PLL_CPUCL1		2

#define CLK_MOUT_CPUCL1_CLUSTER_USER	3

#define CLK_MOUT_CPUCL1_SWITCH_USER	4

#define CLK_MOUT_CPUCL1_CLUSTER		5

#define CLK_MOUT_CPUCL1_CORE		6



#define CLK_DOUT_CLUSTER1_ACLK		7

#define CLK_DOUT_CLUSTER1_ATCLK		8

#define CLK_DOUT_CLUSTER1_MPCLK		9

#define CLK_DOUT_CLUSTER1_PCLK		10

#define CLK_DOUT_CLUSTER1_PERIPHCLK	11

#define CLK_DOUT_CPUCL1_NOCP		12



/* CMU_CPUCL2 */

#define CLK_FOUT_CPUCL2_PLL		1



#define CLK_MOUT_PLL_CPUCL2		2

#define CLK_MOUT_CPUCL2_CLUSTER_USER	3

#define CLK_MOUT_CPUCL2_SWITCH_USER	4

#define CLK_MOUT_CPUCL2_CLUSTER		5

#define CLK_MOUT_CPUCL2_CORE		6



#define CLK_DOUT_CLUSTER2_ACLK		7

#define CLK_DOUT_CLUSTER2_ATCLK		8

#define CLK_DOUT_CLUSTER2_MPCLK		9

#define CLK_DOUT_CLUSTER2_PCLK		10

#define CLK_DOUT_CLUSTER2_PERIPHCLK	11

#define CLK_DOUT_CPUCL2_NOCP		12



/* CMU_PERIC0 */

#define CLK_MOUT_PERIC0_IP_USER		1

#define CLK_MOUT_PERIC0_NOC_USER	2