Commit 22513c0d authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

arm64: sysreg: Add layout for ICH_HCR_EL2 



The ICH_HCR_EL2-related macros are missing a number of control
bits that we are about to handle. Take this opportunity to fully
describe the layout of that register as part of the automatic
generation infrastructure.

This results in a bit of churn, unfortunately.

Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250225172930.1850838-2-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 0ad2507d

arch/arm64/include/asm/sysreg.h

+0 −12
Original line number Diff line number Diff line
@@ -562,7 +562,6 @@ 


#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)

#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)

#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)

#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)

#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
@@ -1003,17 +1002,6 @@ 
#define ICH_LR_PRIORITY_SHIFT	48

#define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)



/* ICH_HCR_EL2 bit definitions */

#define ICH_HCR_EN		(1 << 0)

#define ICH_HCR_UIE		(1 << 1)

#define ICH_HCR_NPIE		(1 << 3)

#define ICH_HCR_TC		(1 << 10)

#define ICH_HCR_TALL0		(1 << 11)

#define ICH_HCR_TALL1		(1 << 12)

#define ICH_HCR_TDIR		(1 << 14)

#define ICH_HCR_EOIcount_SHIFT	27

#define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)



/* ICH_VMCR_EL2 bit definitions */

#define ICH_VMCR_ACK_CTL_SHIFT	2

#define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)

arch/arm64/kvm/emulate-nested.c

+8 −8
Original line number Diff line number Diff line
@@ -412,26 +412,26 @@ static const struct trap_bits coarse_trap_bits[] = { 
	},

	[CGT_ICH_HCR_TC] = {

		.index		= ICH_HCR_EL2,

		.value		= ICH_HCR_TC,

		.mask		= ICH_HCR_TC,

		.value		= ICH_HCR_EL2_TC,

		.mask		= ICH_HCR_EL2_TC,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

	[CGT_ICH_HCR_TALL0] = {

		.index		= ICH_HCR_EL2,

		.value		= ICH_HCR_TALL0,

		.mask		= ICH_HCR_TALL0,

		.value		= ICH_HCR_EL2_TALL0,

		.mask		= ICH_HCR_EL2_TALL0,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

	[CGT_ICH_HCR_TALL1] = {

		.index		= ICH_HCR_EL2,

		.value		= ICH_HCR_TALL1,

		.mask		= ICH_HCR_TALL1,

		.value		= ICH_HCR_EL2_TALL1,

		.mask		= ICH_HCR_EL2_TALL1,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

	[CGT_ICH_HCR_TDIR] = {

		.index		= ICH_HCR_EL2,

		.value		= ICH_HCR_TDIR,

		.mask		= ICH_HCR_TDIR,

		.value		= ICH_HCR_EL2_TDIR,

		.mask		= ICH_HCR_EL2_TDIR,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

};

arch/arm64/kvm/hyp/vgic-v3-sr.c

+7 −7
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if) 


		elrsr = read_gicreg(ICH_ELRSR_EL2);



		write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);

		write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EL2_En, ICH_HCR_EL2);



		for (i = 0; i < used_lrs; i++) {

			if (elrsr & (1 << i))
@@ -274,7 +274,7 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if) 
	 * system registers to trap to EL1 (duh), force ICC_SRE_EL1.SRE to 1

	 * so that the trap bits can take effect. Yes, we *loves* the GIC.

	 */

	if (!(cpu_if->vgic_hcr & ICH_HCR_EN)) {

	if (!(cpu_if->vgic_hcr & ICH_HCR_EL2_En)) {

		write_gicreg(ICC_SRE_EL1_SRE, ICC_SRE_EL1);

		isb();

	} else if (!cpu_if->vgic_sre) {
@@ -752,7 +752,7 @@ static void __vgic_v3_bump_eoicount(void) 
	u32 hcr;



	hcr = read_gicreg(ICH_HCR_EL2);

	hcr += 1 << ICH_HCR_EOIcount_SHIFT;

	hcr += 1 << ICH_HCR_EL2_EOIcount_SHIFT;

	write_gicreg(hcr, ICH_HCR_EL2);

}
@@ -1069,7 +1069,7 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu, 
	case SYS_ICC_EOIR0_EL1:

	case SYS_ICC_HPPIR0_EL1:

	case SYS_ICC_IAR0_EL1:

		return ich_hcr & ICH_HCR_TALL0;

		return ich_hcr & ICH_HCR_EL2_TALL0;



	case SYS_ICC_IGRPEN1_EL1:

		if (is_read &&
@@ -1090,10 +1090,10 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu, 
	case SYS_ICC_EOIR1_EL1:

	case SYS_ICC_HPPIR1_EL1:

	case SYS_ICC_IAR1_EL1:

		return ich_hcr & ICH_HCR_TALL1;

		return ich_hcr & ICH_HCR_EL2_TALL1;



	case SYS_ICC_DIR_EL1:

		if (ich_hcr & ICH_HCR_TDIR)

		if (ich_hcr & ICH_HCR_EL2_TDIR)

			return true;



		fallthrough;
@@ -1101,7 +1101,7 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu, 
	case SYS_ICC_RPR_EL1:

	case SYS_ICC_CTLR_EL1:

	case SYS_ICC_PMR_EL1:

		return ich_hcr & ICH_HCR_TC;

		return ich_hcr & ICH_HCR_EL2_TC;



	default:

		return false;

arch/arm64/kvm/vgic/vgic-v3.c

+9 −8
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) 
{

	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;



	cpuif->vgic_hcr |= ICH_HCR_UIE;

	cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;

}



static bool lr_signals_eoi_mi(u64 lr_val)
@@ -42,7 +42,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) 


	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());



	cpuif->vgic_hcr &= ~ICH_HCR_UIE;

	cpuif->vgic_hcr &= ~ICH_HCR_EL2_UIE;



	for (lr = 0; lr < cpuif->used_lrs; lr++) {

		u64 val = cpuif->vgic_lr[lr];
@@ -292,7 +292,7 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) 
					    ICH_VTR_PRI_BITS_SHIFT) + 1;



	/* Get the show on the road... */

	vgic_v3->vgic_hcr = ICH_HCR_EN;

	vgic_v3->vgic_hcr = ICH_HCR_EL2_En;

}



void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
@@ -301,18 +301,19 @@ void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu) 


	/* Hide GICv3 sysreg if necessary */

	if (!kvm_has_gicv3(vcpu->kvm)) {

		vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC;

		vgic_v3->vgic_hcr |= (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |

				      ICH_HCR_EL2_TC);

		return;

	}



	if (group0_trap)

		vgic_v3->vgic_hcr |= ICH_HCR_TALL0;

		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL0;

	if (group1_trap)

		vgic_v3->vgic_hcr |= ICH_HCR_TALL1;

		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL1;

	if (common_trap)

		vgic_v3->vgic_hcr |= ICH_HCR_TC;

		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TC;

	if (dir_trap)

		vgic_v3->vgic_hcr |= ICH_HCR_TDIR;

		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TDIR;

}



int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)

arch/arm64/tools/sysreg

+22 −0
Original line number Diff line number Diff line
@@ -3035,6 +3035,28 @@ Field 31:16 PhyPARTID29 
Field	15:0	PhyPARTID28

EndSysreg



Sysreg	ICH_HCR_EL2	3	4	12	11	0

Res0	63:32

Field	31:27	EOIcount

Res0	26:16

Field	15	DVIM

Field	14	TDIR

Field	13	TSEI

Field	12	TALL1

Field	11	TALL0

Field	10	TC

Res0	9

Field	8	vSGIEOICount

Field	7	VGrp1DIE

Field	6	VGrp1EIE

Field	5	VGrp0DIE

Field	4	VGrp0EIE

Field	3	NPIE

Field	2	LRENPIE

Field	1	UIE

Field	0	En

EndSysreg



Sysreg	CONTEXTIDR_EL2	3	4	13	0	1

Fields	CONTEXTIDR_ELx

EndSysreg