Commit 2257fac9 authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC 



Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: default avatarSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/8374f407386209d2e7891763de3fa2450a14ad60.1615832893.git.saiprakash.ranjan@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 0392968d

arch/arm64/boot/dts/qcom/sc7280.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/clock/qcom,gcc-sc7280.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -282,6 +283,15 @@ gcc: clock-controller@100000 { 
			#power-domain-cells = <1>;

		};



		ipcc: mailbox@408000 {

			compatible = "qcom,sc7280-ipcc", "qcom,ipcc";

			reg = <0 0x00408000 0 0x1000>;

			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <3>;

			#mbox-cells = <2>;

		};



		qupv3_id_0: geniqup@9c0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0 0x009c0000 0 0x2000>;