Commit 22625d19 authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c 



Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.

v2: Remove from common header in include and use display_regs.h (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-14-uma.shankar@intel.com
parent a8454813

drivers/gpu/drm/i915/display/g4x_hdmi.c

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#include <drm/drm_print.h>



#include "g4x_hdmi.h"

#include "i915_reg.h"

#include "intel_atomic.h"

#include "intel_audio.h"

#include "intel_connector.h"

drivers/gpu/drm/i915/display/intel_display_regs.h

+12 −0
Original line number Diff line number Diff line
@@ -2144,6 +2144,18 @@ 
#define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)

#define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)



/* Icelake PPS_DATA and _ECC DIP Registers.

 * These are available for transcoders B,C and eDP.

 * Adding the _A so as to reuse the _MMIO_TRANS2

 * definition, with which it offsets to the right location.

 */



#define _TRANSA_CHICKEN1	 0xf0060

#define _TRANSB_CHICKEN1	 0xf1060

#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)

#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)

#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)



#define _TRANSA_CHICKEN2	0xf0064

#define _TRANSB_CHICKEN2	0xf1064

#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

drivers/gpu/drm/i915/i915_reg.h

+0 −12
Original line number Diff line number Diff line
@@ -836,18 +836,6 @@ 
#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)





/* Icelake PPS_DATA and _ECC DIP Registers.

 * These are available for transcoders B,C and eDP.

 * Adding the _A so as to reuse the _MMIO_TRANS2

 * definition, with which it offsets to the right location.

 */



#define _TRANSA_CHICKEN1	 0xf0060

#define _TRANSB_CHICKEN1	 0xf1060

#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)

#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)

#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)



#define  VLV_PMWGICZ				_MMIO(0x1300a4)



#define  HSW_EDRAM_CAP				_MMIO(0x120010)