Commit 226fa3ab authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/cx0: Program vswing only for owned lanes 



According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.

BSpec: 74103, 74104
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-5-gustavo.sousa@intel.com
parent 6a62986b

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+14 −11
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	const struct intel_ddi_buf_trans *trans;

	enum phy phy = intel_port_to_phy(i915, encoder->port);

	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);

	intel_wakeref_t wakeref;

	int n_entries, ln;
@@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 
	}



	if (intel_is_c10phy(i915, phy)) {

		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),

			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);

		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),

			      C10_CMN3_TXVBOOST_MASK,

			      C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),

			      MB_WRITE_UNCOMMITTED);

		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1),

			      C10_TX1_TERMCTL_MASK,

			      C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),

			      MB_WRITE_COMMITTED);
@@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 


	for (ln = 0; ln < crtc_state->lane_count; ln++) {

		int level = intel_ddi_level(encoder, crtc_state, ln);

		int lane, tx;

		int lane = ln / 2;

		int tx = ln % 2;

		u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;



		lane = ln / 2;

		tx = ln % 2;

		if (!(lane_mask & owned_lane_mask))

			continue;



		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),

		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),

			      C10_PHY_OVRD_LEVEL_MASK,

			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),

			      MB_WRITE_COMMITTED);

		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),

		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),

			      C10_PHY_OVRD_LEVEL_MASK,

			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),

			      MB_WRITE_COMMITTED);

		intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),

		intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),

			      C10_PHY_OVRD_LEVEL_MASK,

			      C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),

			      MB_WRITE_COMMITTED);

	}



	/* Write Override enables in 0xD71 */

	intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,

	intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,

		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,

		      MB_WRITE_COMMITTED);



	if (intel_is_c10phy(i915, phy))

		intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),

			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);



	intel_cx0_phy_transaction_end(encoder, wakeref);