Commit 227bcf2c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-next-fixes-2025-03-27' of... 

Merge tag 'drm-xe-next-fixes-2025-03-27' of https://gitlab.freedesktop.org/drm/xe/kernel

 into drm-next

Driver Changes:
- Fix NULL pointer dereference on error path
- Add missing HW workaround for BMG
- Fix survivability mode not triggering
- Fix build warning when DRM_FBDEV_EMULATION is not set

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/vxy5kwdkzgp2u2umnyxv4ygslmdlvzjl22xotzxaw55dv7plpz@34miqxkbvggu
parents 41ae768a 5e66cf6e

drivers/gpu/drm/xe/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ config DRM_XE 
config DRM_XE_DISPLAY

	bool "Enable display support"

	depends on DRM_XE && DRM_XE=m && HAS_IOPORT

	select FB_IOMEM_HELPERS

	select FB_IOMEM_HELPERS if DRM_FBDEV_EMULATION

	select I2C

	select I2C_ALGOBIT

	default y

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -130,6 +130,10 @@ 
#define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)



#define RING_IDLEDLY(base)			XE_REG((base) + 0x23c)

#define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)

#define   IDLE_DELAY				REG_GENMASK(20, 0)



#define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)

#define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)

#define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)

drivers/gpu/drm/xe/xe_device.c

+15 −2
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#include "xe_pxp.h"

#include "xe_query.h"

#include "xe_shrinker.h"

#include "xe_survivability_mode.h"

#include "xe_sriov.h"

#include "xe_tile.h"

#include "xe_ttm_stolen_mgr.h"
@@ -705,9 +706,21 @@ int xe_device_probe_early(struct xe_device *xe) 
	sriov_update_device_info(xe);



	err = xe_pcode_probe_early(xe);

	if (err) {

		int save_err = err;



		/*

		 * Try to leave device in survivability mode if device is

		 * possible, but still return the previous error for error

		 * propagation

		 */

		err = xe_survivability_mode_enable(xe);

		if (err)

			return err;



		return save_err;

	}



	err = wait_for_lmem_ready(xe);

	if (err)

		return err;

drivers/gpu/drm/xe/xe_eu_stall.c

+1 −7
Original line number Diff line number Diff line
@@ -222,13 +222,7 @@ int xe_eu_stall_init(struct xe_gt *gt) 
		goto exit_free;

	}



	ret = devm_add_action_or_reset(xe->drm.dev, xe_eu_stall_fini, gt);

	if (ret)

		goto exit_destroy;



	return 0;

exit_destroy:

	destroy_workqueue(gt->eu_stall->buf_ptr_poll_wq);

	return devm_add_action_or_reset(xe->drm.dev, xe_eu_stall_fini, gt);

exit_free:

	mutex_destroy(&gt->eu_stall->stream_lock);

	kfree(gt->eu_stall);

drivers/gpu/drm/xe/xe_gt_clock.c

+38 −16
Original line number Diff line number Diff line
@@ -16,35 +16,47 @@ 
#include "xe_macros.h"

#include "xe_mmio.h"



static u32 get_crystal_clock_freq(u32 rpm_config_reg)

#define f19_2_mhz	19200000

#define f24_mhz		24000000

#define f25_mhz		25000000

#define f38_4_mhz	38400000

#define ts_base_83	83333

#define ts_base_52	52083

#define ts_base_80	80000



static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,

			       u32 *timestamp_base)

{

	const u32 f19_2_mhz = 19200000;

	const u32 f24_mhz = 24000000;

	const u32 f25_mhz = 25000000;

	const u32 f38_4_mhz = 38400000;

	u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,

					  rpm_config_reg);



	switch (crystal_clock) {

	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:

		return f24_mhz;

		*freq = f24_mhz;

		*timestamp_base = ts_base_83;

		return;

	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:

		return f19_2_mhz;

		*freq = f19_2_mhz;

		*timestamp_base = ts_base_52;

		return;

	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:

		return f38_4_mhz;

		*freq = f38_4_mhz;

		*timestamp_base = ts_base_52;

		return;

	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:

		return f25_mhz;

		*freq = f25_mhz;

		*timestamp_base = ts_base_80;

		return;

	default:

		XE_WARN_ON("NOT_POSSIBLE");

		return 0;

		xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);

		*freq = 0;

		*timestamp_base = 0;

		return;

	}

}



int xe_gt_clock_init(struct xe_gt *gt)

static void check_ctc_mode(struct xe_gt *gt)

{

	u32 c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);

	u32 freq = 0;



	/*

	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later

	 * platforms.  In theory it could be a valid setting for pre-Xe2
@@ -57,8 +69,18 @@ int xe_gt_clock_init(struct xe_gt *gt) 
	 */

	if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)

		xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");

}



int xe_gt_clock_init(struct xe_gt *gt)

{

	u32 freq;

	u32 c0;



	if (!IS_SRIOV_VF(gt_to_xe(gt)))

		check_ctc_mode(gt);



	freq = get_crystal_clock_freq(c0);

	c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);

	read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);



	/*

	 * Now figure out how the command stream's timestamp