Commit 2284cca0 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: ingenic: simplify x2000 mac_set_mode() 



As per the previous commit, we have validated that the phy_intf_sel
value is one that is permissible for this SoC, so there is no need to
handle invalid PHY interface modes. We can also apply the other
configuration based upon the phy_intf_sel value rather than the
PHY interface mode.

Reviewed-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vHHqO-0000000Djrb-0DPN@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 608975d4

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

+7 −21
Original line number Diff line number Diff line
@@ -122,17 +122,12 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat, 
	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |

			  FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);

		break;

	val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);



	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		val = 0;

	if (phy_intf_sel == PHY_INTF_SEL_RMII) {

		val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |

		       FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);

	} else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {

		if (mac->tx_delay == 0)

			val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);

		else
@@ -144,17 +139,8 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat, 
		else

			val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |

				   FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);



		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}



	val |= FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}