Commit 22eaa206 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-simplify-axi_blen-handling' 

Russell King says:

====================
net: stmmac: simplify axi_blen handling

stmmac's axi_blen (burst length) handling is very verbose and
unnecessary.

Firstly, the burst length register bitfield is the same across all
dwmac cores, so we can use common definitions for these bits which
platform glue can use.

We end up with platform glue:
- filling in the axi_blen[] array with the decimal burst lengths, e.g.
  dwmac-intel.c, etc
- decoding a bitmap into burst lengths for this array, e.g.
  dwmac-dwc-qos-eth.c

Other cases read the array from DT, placing it into the axi_blen
array, and converting later to the register bitfield.

This series removes all this complexity, ultimately ending up with
platform glue providing the register value containing the burst
length bitfield directly. Where necessary, platform glue calls
stmmac_axi_blen_to_mask() to convert a decimal array (e.g. from
DT) to the register value.

This also means that stmmac_axi_blen_to_mask() can issue a
diagnostic message at probe time if the burst length is incorrect.
====================

Link: https://patch.msgid.link/aR2aaDs6rqfu32B-@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents f15bcd07 efd3c8cc

drivers/net/ethernet/stmicro/stmmac/common.h

+13 −0
Original line number Diff line number Diff line
@@ -548,6 +548,19 @@ struct dma_features { 
#define LPI_CTRL_STATUS_TLPIEX	BIT(1)	/* Transmit LPI Exit */

#define LPI_CTRL_STATUS_TLPIEN	BIT(0)	/* Transmit LPI Entry */



/* Common definitions for AXI Master Bus Mode */

#define DMA_AXI_AAL		BIT(12)

#define DMA_AXI_BLEN256		BIT(7)

#define DMA_AXI_BLEN128		BIT(6)

#define DMA_AXI_BLEN64		BIT(5)

#define DMA_AXI_BLEN32		BIT(4)

#define DMA_AXI_BLEN16		BIT(3)

#define DMA_AXI_BLEN8		BIT(2)

#define DMA_AXI_BLEN4		BIT(1)

#define DMA_AXI_BLEN_MASK	GENMASK(7, 1)



void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len);



#define STMMAC_CHAIN_MODE	0x1

#define STMMAC_RING_MODE	0x2

drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c

+2 −26
Original line number Diff line number Diff line
@@ -38,8 +38,6 @@ static int dwc_eth_dwmac_config_dt(struct platform_device *pdev, 
{

	struct device *dev = &pdev->dev;

	u32 burst_map = 0;

	u32 bit_index = 0;

	u32 a_index = 0;



	if (!plat_dat->axi) {

		plat_dat->axi = devm_kzalloc(&pdev->dev,
@@ -83,30 +81,8 @@ static int dwc_eth_dwmac_config_dt(struct platform_device *pdev, 
	}

	device_property_read_u32(dev, "snps,burst-map", &burst_map);



	/* converts burst-map bitmask to burst array */

	for (bit_index = 0; bit_index < 7; bit_index++) {

		if (burst_map & (1 << bit_index)) {

			switch (bit_index) {

			case 0:

			plat_dat->axi->axi_blen[a_index] = 4; break;

			case 1:

			plat_dat->axi->axi_blen[a_index] = 8; break;

			case 2:

			plat_dat->axi->axi_blen[a_index] = 16; break;

			case 3:

			plat_dat->axi->axi_blen[a_index] = 32; break;

			case 4:

			plat_dat->axi->axi_blen[a_index] = 64; break;

			case 5:

			plat_dat->axi->axi_blen[a_index] = 128; break;

			case 6:

			plat_dat->axi->axi_blen[a_index] = 256; break;

			default:

			break;

			}

			a_index++;

		}

	}

	plat_dat->axi->axi_blen_regval = FIELD_PREP(DMA_AXI_BLEN_MASK,

						    burst_map);



	/* dwc-qos needs GMAC4, AAL, TSO and PMT */

	plat_dat->core_type = DWMAC_CORE_GMAC4;

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+2 −3
Original line number Diff line number Diff line
@@ -650,9 +650,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, 
	plat->axi->axi_xit_frm = 0;

	plat->axi->axi_wr_osr_lmt = 1;

	plat->axi->axi_rd_osr_lmt = 1;

	plat->axi->axi_blen[0] = 4;

	plat->axi->axi_blen[1] = 8;

	plat->axi->axi_blen[2] = 16;

	plat->axi->axi_blen_regval = DMA_AXI_BLEN4 | DMA_AXI_BLEN8 |

				     DMA_AXI_BLEN16;



	plat->ptp_max_adj = plat->clk_ptp_rate;

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+3 −27
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ 
static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)

{

	u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);

	int i;



	pr_info("dwmac1000: Master AXI performs %s burst length\n",

		!(value & DMA_AXI_UNDEF) ? "fixed" : "any");
@@ -39,33 +38,10 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 


	/* Depending on the UNDEF bit the Master AXI will perform any burst

	 * length according to the BLEN programmed (by default all BLEN are

	 * set).

	 * set). Note that the UNDEF bit is readonly, and is the inverse of

	 * Bus Mode bit 16.

	 */

	for (i = 0; i < AXI_BLEN; i++) {

		switch (axi->axi_blen[i]) {

		case 256:

			value |= DMA_AXI_BLEN256;

			break;

		case 128:

			value |= DMA_AXI_BLEN128;

			break;

		case 64:

			value |= DMA_AXI_BLEN64;

			break;

		case 32:

			value |= DMA_AXI_BLEN32;

			break;

		case 16:

			value |= DMA_AXI_BLEN16;

			break;

		case 8:

			value |= DMA_AXI_BLEN8;

			break;

		case 4:

			value |= DMA_AXI_BLEN4;

			break;

		}

	}

	value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;



	writel(value, ioaddr + DMA_AXI_BUS_MODE);

}

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

+3 −27
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)

{

	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);

	int i;



	pr_info("dwmac4: Master AXI performs %s burst length\n",

		(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
@@ -38,33 +37,10 @@ static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 


	/* Depending on the UNDEF bit the Master AXI will perform any burst

	 * length according to the BLEN programmed (by default all BLEN are

	 * set).

	 * set). Note that the UNDEF bit is readonly, and is the inverse of

	 * Bus Mode bit 16.

	 */

	for (i = 0; i < AXI_BLEN; i++) {

		switch (axi->axi_blen[i]) {

		case 256:

			value |= DMA_AXI_BLEN256;

			break;

		case 128:

			value |= DMA_AXI_BLEN128;

			break;

		case 64:

			value |= DMA_AXI_BLEN64;

			break;

		case 32:

			value |= DMA_AXI_BLEN32;

			break;

		case 16:

			value |= DMA_AXI_BLEN16;

			break;

		case 8:

			value |= DMA_AXI_BLEN8;

			break;

		case 4:

			value |= DMA_AXI_BLEN4;

			break;

		}

	}

	value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;



	writel(value, ioaddr + DMA_SYS_BUS_MODE);

}