Commit 23028286 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Peter Zijlstra
Browse files

x86/apic: Avoid the PVOPS indirection for the TSC deadline timer 



XEN PV does not emulate the TSC deadline timer, so the PVOPS indirection
for writing the deadline MSR can be avoided completely.

Use native_wrmsrq() instead.

Signed-off-by: default avatarThomas Gleixner <tglx@kernel.org>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260224163429.877429827@kernel.org
parent 92d0e753

arch/x86/kernel/apic/apic.c

+10 −3
Original line number Diff line number Diff line
@@ -426,7 +426,7 @@ static int lapic_next_deadline(unsigned long delta, struct clock_event_device *e 
	 */

	u64 tsc = rdtsc();



	wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));

	native_wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));

	return 0;

}
@@ -450,7 +450,7 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) 
	 * the timer _and_ zero the counter registers:

	 */

	if (v & APIC_LVT_TIMER_TSCDEADLINE)

		wrmsrq(MSR_IA32_TSC_DEADLINE, 0);

		native_wrmsrq(MSR_IA32_TSC_DEADLINE, 0);

	else

		apic_write(APIC_TMICT, 0);
@@ -547,6 +547,11 @@ static __init bool apic_validate_deadline_timer(void) 


	if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))

		return false;



	/* XEN_PV does not support it, but be paranoia about it */

	if (boot_cpu_has(X86_FEATURE_XENPV))

		goto clear;



	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))

		return true;
@@ -559,9 +564,11 @@ static __init bool apic_validate_deadline_timer(void) 
	if (boot_cpu_data.microcode >= rev)

		return true;



	setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);

	pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "

	       "please update microcode to version: 0x%x (or later)\n", rev);



clear:

	setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);

	return false;

}