Commit 23029150 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: Optimize PLL table memory usage 



Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696

In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 6efb943b

drivers/clk/rockchip/clk.h

+18 −11
Original line number Diff line number Diff line
@@ -271,10 +271,15 @@ struct rockchip_clk_provider { 


struct rockchip_pll_rate_table {

	unsigned long rate;

	union {

		struct {

			/* for RK3066 */

			unsigned int nr;

			unsigned int nf;

			unsigned int no;

			unsigned int nb;

		};

		struct {

			/* for RK3036/RK3399 */

			unsigned int fbdiv;

			unsigned int postdiv1;
@@ -283,6 +288,8 @@ struct rockchip_pll_rate_table { 
			unsigned int dsmpd;

			unsigned int frac;

		};

	};

};



/**

 * struct rockchip_pll_clock - information about pll clock