Commit 231b1d6c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dsb: Don't use indexed writes when byte enables are not all set 



The indexed write instruction doesn't support byte-enables, so
if the non-indexed write used those we must not convert it to
an indexed write.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-8-ville.syrjala@linux.intel.com


Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
parent 088ca021

drivers/gpu/drm/i915/display/intel_dsb.c

+9 −3
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, 
	if (dsb->free_pos == 0)

		return false;



	prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT;

	prev_opcode = buf[dsb->ins_start_offset + 1] & ~DSB_REG_VALUE_MASK;

	prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;



	return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
@@ -153,12 +153,18 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, 


static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg)

{

	return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg);

	/* only full byte-enables can be converted to indexed writes */

	return intel_dsb_prev_ins_is_write(dsb,

					   DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT |

					   DSB_BYTE_EN << DSB_BYTE_EN_SHIFT,

					   reg);

}



static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)

{

	return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg);

	return intel_dsb_prev_ins_is_write(dsb,

					   DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT,

					   reg);

}



/**