Commit 232269eb authored by Oliver Upton's avatar Oliver Upton Committed by Marc Zyngier
Browse files

KVM: selftests: Add quadword MMIO accessors 



The base registers in the GIC ITS and redistributor for LPIs are 64 bits
wide. Add quadword accessors to poke at them.

Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240422200158.2606761-16-oliver.upton@linux.dev


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 1505bc70

tools/testing/selftests/kvm/include/aarch64/processor.h

+17 −0
Original line number Diff line number Diff line
@@ -177,11 +177,28 @@ static __always_inline u32 __raw_readl(const volatile void *addr) 
	return val;

}



static __always_inline void __raw_writeq(u64 val, volatile void *addr)

{

	asm volatile("str %0, [%1]" : : "rZ" (val), "r" (addr));

}



static __always_inline u64 __raw_readq(const volatile void *addr)

{

	u64 val;

	asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));

	return val;

}



#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))

#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })

#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))

#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })



#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c));})

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })

#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c));})

#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })





static inline void local_irq_enable(void)

{