Commit 23444132 authored by Nicholas Susanto's avatar Nicholas Susanto Committed by Alex Deucher
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drm/amd/display: DCN35 set min dispclk to 50Mhz



[Why]

Causes hard hangs when resuming after display off on extended/duplicate
modes

[How]

Set the min dispclk to 50Mhz for DCN35

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarNicholas Susanto <Nicholas.Susanto@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ec9e2e7a
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+3 −0
Original line number Diff line number Diff line
@@ -305,6 +305,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
	if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
		new_clocks->ref_dtbclk_khz = 600000;

	if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
		new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;

	/*
	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
	 * also if safe to lower is false, we just go in the higher state
+1 −0
Original line number Diff line number Diff line
@@ -786,6 +786,7 @@ static const struct dc_debug_options debug_defaults_drv = {
	.disable_dmub_reallow_idle = false,
	.static_screen_wait_frames = 2,
	.disable_timeout = true,
	.min_disp_clk_khz = 50000,
};

static const struct dc_panel_config panel_config_defaults = {