Commit 2374b99e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: align clocks in I2C/SPI with DT schema 



The DT schema expects clocks core-iface order.  No functional change.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
parent 0e1b27f4

arch/arm64/boot/dts/qcom/ipq6018.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -318,9 +318,9 @@ i2c_0: i2c@78b6000 { 
			#size-cells = <0>;

			reg = <0x0 0x078b6000 0x0 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency  = <400000>;

			dmas = <&blsp_dma 14>, <&blsp_dma 15>;

			dma-names = "tx", "rx";
@@ -333,9 +333,9 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 
			#size-cells = <0>;

			reg = <0x0 0x078b7000 0x0 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency  = <400000>;

			dmas = <&blsp_dma 16>, <&blsp_dma 17>;

			dma-names = "tx", "rx";

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -467,9 +467,9 @@ blsp1_i2c2: i2c@78b6000 { 
			#size-cells = <0>;

			reg = <0x078b6000 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp_dma 14>, <&blsp_dma 15>;

			dma-names = "tx", "rx";
@@ -484,9 +484,9 @@ blsp1_i2c3: i2c@78b7000 { 
			#size-cells = <0>;

			reg = <0x078b7000 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <100000>;

			dmas = <&blsp_dma 16>, <&blsp_dma 17>;

			dma-names = "tx", "rx";
@@ -499,9 +499,9 @@ blsp1_i2c5: i2c@78b9000 { 
			#size-cells = <0>;

			reg = <0x78b9000 0x600>;

			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp_dma 20>, <&blsp_dma 21>;

			dma-names = "tx", "rx";
@@ -514,9 +514,9 @@ blsp1_i2c6: i2c@78ba000 { 
			#size-cells = <0>;

			reg = <0x078ba000 0x600>;

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <100000>;

			dmas = <&blsp_dma 22>, <&blsp_dma 23>;

			dma-names = "tx", "rx";

arch/arm64/boot/dts/qcom/msm8916.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -1511,9 +1511,9 @@ blsp_i2c1: i2c@78b5000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b5000 0x500>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c1_default>;

			pinctrl-1 = <&i2c1_sleep>;
@@ -1543,9 +1543,9 @@ blsp_i2c2: i2c@78b6000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b6000 0x500>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c2_default>;

			pinctrl-1 = <&i2c2_sleep>;
@@ -1575,9 +1575,9 @@ blsp_i2c3: i2c@78b7000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b7000 0x500>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c3_default>;

			pinctrl-1 = <&i2c3_sleep>;
@@ -1607,9 +1607,9 @@ blsp_i2c4: i2c@78b8000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b8000 0x500>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c4_default>;

			pinctrl-1 = <&i2c4_sleep>;
@@ -1639,9 +1639,9 @@ blsp_i2c5: i2c@78b9000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b9000 0x500>;

			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c5_default>;

			pinctrl-1 = <&i2c5_sleep>;
@@ -1671,9 +1671,9 @@ blsp_i2c6: i2c@78ba000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078ba000 0x500>;

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c6_default>;

			pinctrl-1 = <&i2c6_sleep>;

arch/arm64/boot/dts/qcom/msm8953.dtsi

+24 −24
Original line number Diff line number Diff line
@@ -923,9 +923,9 @@ i2c_1: i2c@78b5000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x78b5000 0x600>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;



			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_1_default>;
@@ -941,9 +941,9 @@ i2c_2: i2c@78b6000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x78b6000 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;



			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_2_default>;
@@ -959,9 +959,9 @@ i2c_3: i2c@78b7000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x78b7000 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_3_default>;

			pinctrl-1 = <&i2c_3_sleep>;
@@ -976,9 +976,9 @@ i2c_4: i2c@78b8000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x78b8000 0x600>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_4_default>;

			pinctrl-1 = <&i2c_4_sleep>;
@@ -993,9 +993,9 @@ i2c_5: i2c@7af5000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x7af5000 0x600>;

			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

				 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_5_default>;

			pinctrl-1 = <&i2c_5_sleep>;
@@ -1010,9 +1010,9 @@ i2c_6: i2c@7af6000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x7af6000 0x600>;

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

				 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_6_default>;

			pinctrl-1 = <&i2c_6_sleep>;
@@ -1027,9 +1027,9 @@ i2c_7: i2c@7af7000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x7af7000 0x600>;

			interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

				 <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_7_default>;

			pinctrl-1 = <&i2c_7_sleep>;
@@ -1044,9 +1044,9 @@ i2c_8: i2c@7af8000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x7af8000 0x600>;

			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

				 <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;

			clock-names = "core", "iface";

			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c_8_default>;

			pinctrl-1 = <&i2c_8_sleep>;

arch/arm64/boot/dts/qcom/msm8994.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -519,9 +519,9 @@ blsp1_i2c1: i2c@f9923000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9923000 0x500>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

						<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;

			dma-names = "tx", "rx";
@@ -555,9 +555,9 @@ blsp1_i2c2: i2c@f9924000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9924000 0x500>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

						<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;

			dma-names = "tx", "rx";
@@ -575,9 +575,9 @@ blsp1_i2c4: i2c@f9926000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9926000 0x500>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

						<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;

			dma-names = "tx", "rx";
@@ -593,9 +593,9 @@ blsp1_i2c5: i2c@f9927000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9927000 0x500>;

			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

						<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;

			dma-names = "tx", "rx";
@@ -611,9 +611,9 @@ blsp1_i2c6: i2c@f9928000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9928000 0x500>;

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

						<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;

			dma-names = "tx", "rx";
@@ -657,9 +657,9 @@ blsp2_i2c1: i2c@f9963000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9963000 0x500>;

			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

					<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;

			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;

			dma-names = "tx", "rx";
@@ -693,9 +693,9 @@ blsp2_i2c5: i2c@f9967000 { 
			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0xf9967000 0x500>;

			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_AHB_CLK>,

						<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <355000>;

			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;

			dma-names = "tx", "rx";