Commit 238352b4 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: Enable bad opcode interrupt 



For the bad opcode case, it will cause CP/ME hang.
The firmware will prevent the ME side from hanging by raising a bad opcode interrupt.
And the driver needs to perform a vmid reset when receiving the interrupt.

Acked-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ebca62e

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+65 −0
Original line number Diff line number Diff line
@@ -2182,6 +2182,13 @@ static int gfx_v9_0_sw_init(void *handle) 
	if (r)

		return r;



	/* Bad opcode Event */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,

			      GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR,

			      &adev->gfx.bad_op_irq);

	if (r)

		return r;



	/* Privileged reg */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,

			      &adev->gfx.priv_reg_irq);
@@ -3937,6 +3944,7 @@ static int gfx_v9_0_hw_fini(void *handle) 
		amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);



	/* DF freeze and kcq disable will fail */

	if (!amdgpu_ras_intr_triggered())
@@ -4747,6 +4755,10 @@ static int gfx_v9_0_late_init(void *handle) 
	if (r)

		return r;



	r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);

	if (r)

		return r;



	r = gfx_v9_0_ecc_late_init(handle);

	if (r)

		return r;
@@ -5990,6 +6002,42 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 
	return 0;

}



static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,

					   struct amdgpu_irq_src *source,

					   unsigned type,

					   enum amdgpu_interrupt_state state)

{

	u32 cp_int_cntl_reg, cp_int_cntl;

	int i, j;



	switch (state) {

	case AMDGPU_IRQ_STATE_DISABLE:

	case AMDGPU_IRQ_STATE_ENABLE:

		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,

			       OPCODE_ERROR_INT_ENABLE,

			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);

		for (i = 0; i < adev->gfx.mec.num_mec; i++) {

			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {

				/* MECs start at 1 */

				cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);



				if (cp_int_cntl_reg) {

					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);

					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

								    OPCODE_ERROR_INT_ENABLE,

								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);

					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

				}

			}

		}

		break;

	default:

		break;

	}



	return 0;

}



static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,

					      struct amdgpu_irq_src *source,

					      unsigned type,
@@ -6163,6 +6211,15 @@ static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 
	return 0;

}



static int gfx_v9_0_bad_op_irq(struct amdgpu_device *adev,

			       struct amdgpu_irq_src *source,

			       struct amdgpu_iv_entry *entry)

{

	DRM_ERROR("Illegal opcode in command stream\n");

	gfx_v9_0_fault(adev, entry);

	return 0;

}



static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,

				  struct amdgpu_irq_src *source,

				  struct amdgpu_iv_entry *entry)
@@ -7346,6 +7403,11 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 
	.process = gfx_v9_0_priv_reg_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v9_0_bad_op_irq_funcs = {

	.set = gfx_v9_0_set_bad_op_fault_state,

	.process = gfx_v9_0_bad_op_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {

	.set = gfx_v9_0_set_priv_inst_fault_state,

	.process = gfx_v9_0_priv_inst_irq,
@@ -7365,6 +7427,9 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 
	adev->gfx.priv_reg_irq.num_types = 1;

	adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;



	adev->gfx.bad_op_irq.num_types = 1;

	adev->gfx.bad_op_irq.funcs = &gfx_v9_0_bad_op_irq_funcs;



	adev->gfx.priv_inst_irq.num_types = 1;

	adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;