Commit 240156b2 authored by Manuel Hernández Méndez's avatar Manuel Hernández Méndez Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events riscv: Add CVA6 JSON file 

This patch add the OpenHW Core-V CVA6 Risc-V JSON file.

For more info:

https://openhwfoundation.org/news/2023/11/07/openhw-group-announces-core-v-cva6-platform-project-for-risc-v-software-development-and-testing/



Signed-off-by: default avatarManuel Hernández Méndez <manuel.hernandez@openchip.com>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent c5574114

tools/perf/pmu-events/arch/riscv/mapfile.csv

+1 −0
Original line number Diff line number Diff line
@@ -21,5 +21,6 @@ 
0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core

0x5b7-0x0-0x0,v1,thead/c900-legacy,core

0x5b7-0x80000000090c0d00-0x2047000,v1,thead/c900-legacy,core

0x602-0x3-0x0,v1,openhwgroup/cva6,core

0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core

0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json

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+68 −0
Original line number Diff line number Diff line 
[

  {

    "ArchStdEvent": "FW_MISALIGNED_LOAD"

  },

  {

    "ArchStdEvent": "FW_MISALIGNED_STORE"

  },

  {

    "ArchStdEvent": "FW_ACCESS_LOAD"

  },

  {

    "ArchStdEvent": "FW_ACCESS_STORE"

  },

  {

    "ArchStdEvent": "FW_ILLEGAL_INSN"

  },

  {

    "ArchStdEvent": "FW_SET_TIMER"

  },

  {

    "ArchStdEvent": "FW_IPI_SENT"

  },

  {

    "ArchStdEvent": "FW_IPI_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_FENCE_I_SENT"

  },

  {

    "ArchStdEvent": "FW_FENCE_I_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_SFENCE_VMA_SENT"

  },

  {

    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"

  },

  {

    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"

  },

  {

    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"

  },

  {

    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"

  },

  {

    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"

  },

  {

    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"

  },

  {

    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"

  }

]

tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json

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+47 −0
Original line number Diff line number Diff line 
[

  {

    "EventName": "LOAD_INSTRUCTIONS_RETIRED",

    "EventCode": "0x5",

    "BriefDescription": "number of data memory load instructions retired"

  },

  {

    "EventName": "STORE_INSTRUCTIONS_RETIRED",

    "EventCode": "0x6",

    "BriefDescription": "number of data memory store instructions retired"

  },

  {

    "EventName": "EXCEPTIONS",

    "EventCode": "0x7",

    "BriefDescription": "valid exceptions encountered"

  },

  {

    "EventName": "EXCEPTION_HANDLER_RETURNS",

    "EventCode": "0x8",

    "BriefDescription": "return from an exception"

  },

  {

    "EventName": "BRANCH_INSTRUCTIONS_RETIRED",

    "EventCode": "0x9",

    "BriefDescription": "number of branch instructions encountered retired"

  },

  {

    "EventName": "CALL_INSTRUCTIONS_RETIRED",

    "EventCode": "0xC",

    "BriefDescription": "number of call instructions retired"

  },

  {

    "EventName": "RETURN_INSTRUCTIONS_RETIRED",

    "EventCode": "0xD",

    "BriefDescription": "number of return instructions retired"

  },

  {

    "EventName": "INTEGER_INSTRUCTIONS_RETIRED",

    "EventCode": "0x14",

    "BriefDescription": "number of integer instructions retired"

  },

  {

    "EventName": "FLOATING_POINT_INSTRUCTIONS_RETIRED",

    "EventCode": "0x15",

    "BriefDescription": "number of floating point instructions retired"

  }

]

tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json

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+42 −0
Original line number Diff line number Diff line 
[

  {

    "EventName": "L1_I_CACHE_MISSES",

    "EventCode": "0x1",

    "BriefDescription": "number of misses in L1 I-Cache"

  },

  {

    "EventName": "L1_D_CACHE_MISSES",

    "EventCode": "0x2",

    "BriefDescription": "number of misses in L1 D-Cache"

  },

  {

    "EventName": "ITLB_MISSES",

    "EventCode": "0x3",

    "BriefDescription": "number of misses in ITLB"

  },

  {

    "EventName": "DTLB_MISSES",

    "EventCode": "0x4",

    "BriefDescription": "number of misses in DTLB"

  },

  {

    "EventName": "L1_I_CACHE_ACCESSES",

    "EventCode": "0x10",

    "BriefDescription": "number of accesses to instruction cache"

  },

  {

    "EventName": "L1_D_CACHE_ACCESSES",

    "EventCode": "0x11",

    "BriefDescription": "number of accesses to data cache"

  },

  {

    "EventName": "L1_CACHE_LINE_EVICTION",

    "EventCode": "0x12",

    "BriefDescription": "number of data cache line eviction"

  },

  {

    "EventName": "ITLB_FLUSH",

    "EventCode": "0x13",

    "BriefDescription": "number of ITLB flushes"

  }

]

tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json

0 → 100644
+27 −0
Original line number Diff line number Diff line 
[

  {

    "EventName": "BRANCH_MISPREDICTS",

    "EventCode": "0xA",

    "BriefDescription": "number of branch mispredictions"

  },

  {

    "EventName": "BRANCH_EXCEPTIONS",

    "EventCode": "0xB",

    "BriefDescription": "number of valid branch exceptions"

  },

  {

    "EventName": "MSB_FULL",

    "EventCode": "0xE",

    "BriefDescription": "scoreboard is full"

  },

  {

    "EventName": "INSTRUCTION_FETCH_EMPTY",

    "EventCode": "0xF",

    "BriefDescription": "number of invalid instructions in IF stage"

  },

  {

    "EventName": "PIPELINE_STALL",

    "EventCode": "0x16",

    "BriefDescription": "number of cycles the pipeline is stalled during read operands"

  }

]