Unverified Commit 244c18fb authored by Andrew Jones's avatar Andrew Jones Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zawrs ISA extension 



Export Zawrs ISA extension through hwprobe.

[Palmer: there's a gap in the numbers here as there will be a merge
conflict when this is picked up.  To avoid confusion I just set the
hwprobe ID to match what it would be post-merge.]

Signed-off-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20240426100820.14762-12-ajones@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b8ddb0df

Documentation/arch/riscv/hwprobe.rst

+4 −0
Original line number Diff line number Diff line
@@ -188,6 +188,10 @@ The following keys are defined: 
       manual starting from commit 95cf1f9 ("Add changes requested by Ved

       during signoff")



  * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as

       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)

#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define		RISCV_HWPROBE_EXT_ZAWRS		(1ULL << 48)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_hwprobe.c

+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZTSO);

		EXT_KEY(ZACAS);

		EXT_KEY(ZICOND);

		EXT_KEY(ZAWRS);



		if (has_vector()) {

			EXT_KEY(ZVBB);