Commit 24773076 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events intel: Update meteorlake events to v1.06 

Update meteorlake from v1.04 to v1.06 adding the changes from:
https://github.com/intel/perfmon/commit/bc84df043091ec7c98c0629f3d074d9d7a108194
https://github.com/intel/perfmon/commit/405d3ee987d756b5b5d9a64d8a8fa77559822ecf



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20231026003149.3287633-6-irogers@google.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent f9418b52

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ GenuineIntel-6-3E,v24,ivytown,core 
GenuineIntel-6-2D,v24,jaketown,core

GenuineIntel-6-(57|85),v16,knightslanding,core

GenuineIntel-6-BD,v1.00,lunarlake,core

GenuineIntel-6-A[AC],v1.04,meteorlake,core

GenuineIntel-6-A[AC],v1.06,meteorlake,core

GenuineIntel-6-1[AEF],v4,nehalemep,core

GenuineIntel-6-2E,v4,nehalemex,core

GenuineIntel-6-A7,v1.01,rocketlake,core

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

+30 −0
Original line number Diff line number Diff line
@@ -966,6 +966,16 @@ 
        "UMask": "0x3",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",

        "EventCode": "0x2A,0x2B",
@@ -976,6 +986,16 @@ 
        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x8003C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",

        "EventCode": "0x2A,0x2B",
@@ -986,6 +1006,16 @@ 
        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",

        "EventCode": "0x2A,0x2B",

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

+25 −4
Original line number Diff line number Diff line
@@ -460,6 +460,27 @@ 
        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",

        "CounterMask": "6",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",

        "CounterMask": "1",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",

        "Invert": "1",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",

        "EventCode": "0x9c",
@@ -470,22 +491,22 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",

        "CounterMask": "6",

        "EventCode": "0x9c",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",

        "CounterMask": "1",

        "EventCode": "0x9c",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

        "Invert": "1",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

tools/perf/pmu-events/arch/x86/meteorlake/memory.json

+37 −0
Original line number Diff line number Diff line
@@ -66,6 +66,14 @@ 
        "UMask": "0x84",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "SampleAfterValue": "20003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",

        "EventCode": "0xc3",
@@ -75,6 +83,15 @@ 
        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

        "CounterMask": "2",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

        "CounterMask": "3",
@@ -279,6 +296,26 @@ 
        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data read requests that miss the L3 cache.",

        "EventCode": "0x21",

tools/perf/pmu-events/arch/x86/meteorlake/other.json

+40 −0
Original line number Diff line number Diff line
@@ -7,6 +7,46 @@ 
        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.DRAM",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x184000001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts streaming stores that have any type of response.",

        "EventCode": "0xB7",

        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10800",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts streaming stores that have any type of response.",

        "EventCode": "0x2A,0x2B",