Commit 24a51f8b authored by Tommaso Merciai's avatar Tommaso Merciai Committed by Geert Uytterhoeven
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clk: renesas: r9a09g047: Add entries for the RSPIs 



Add clock and reset entries for the Renesas RZ/G3E RSPI IPs.

Signed-off-by: default avatarTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/ca59fdcc6c32b8f6659aa9218f1a42d2bcd258c3.1771344527.git.tommaso.merciai.xr@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c8d5972a

drivers/clk/renesas/r9a09g047-cpg.c

+24 −0
Original line number Diff line number Diff line
@@ -224,6 +224,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -457,6 +475,12 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */

	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */

	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */

	DEF_RST(7, 14, 3, 15),		/* RSPI_1_TRESETN */

	DEF_RST(7, 15, 3, 16),		/* RSPI_2_PRESETN */

	DEF_RST(8, 0, 3, 17),		/* RSPI_2_TRESETN */

	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */

	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */

	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */