Commit 24c61d55 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2025-01-07' of gitlab.freedesktop.org:drm/msm into drm-next 



Updates for v6.14

MDSS:
- properly described UBWC registers
- added SM6150 (aka QCS615) support

MDP4:
- several small fixes

DPU:
- added SM6150 (aka QCS615) support
- enabled wide planes if virtual planes are enabled (by using two SSPPs for a single plane)
- fixed modes filtering for platforms w/o 3DMux
- fixed DSPP DSPP_2 / _3 links on several platforms
- corrected DSPP definitions on SDM670
- added CWB hardware blocks support
- added VBIF to DPU snapshots
- dropped struct dpu_rm_requirements

DP:
- reworked DP audio support

DSI:
- added SM6150 (aka QCS615) support

GPU:
- Print GMU core fw version
- GMU bandwidth voting for a740 and a750
- Expose uche trap base via uapi
- UAPI error reporting

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsutUu4ff6OpXNXxqf1xaV0rV6oV23VXNRiF0_OEfe72Q@mail.gmail.com
parents c3d590f8 866e43b9

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

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Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: MSM Display Port Controller 


maintainers:

  - Kuogee Hsieh <quic_khsieh@quicinc.com>

  - Abhinav Kumar <quic_abhinavk@quicinc.com>



description: |

  Device tree bindings for DisplayPort host controller for MSM targets

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

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@@ -30,6 +30,7 @@ properties: 
              - qcom,sdm845-dsi-ctrl

              - qcom,sm6115-dsi-ctrl

              - qcom,sm6125-dsi-ctrl

              - qcom,sm6150-dsi-ctrl

              - qcom,sm6350-dsi-ctrl

              - qcom,sm6375-dsi-ctrl

              - qcom,sm7150-dsi-ctrl
@@ -349,6 +350,7 @@ allOf: 
            enum:

              - qcom,sc7180-dsi-ctrl

              - qcom,sc7280-dsi-ctrl

              - qcom,sm6150-dsi-ctrl

              - qcom,sm7150-dsi-ctrl

              - qcom,sm8150-dsi-ctrl

              - qcom,sm8250-dsi-ctrl

Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml

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@@ -20,6 +20,7 @@ properties: 
      - qcom,dsi-phy-14nm-660

      - qcom,dsi-phy-14nm-8953

      - qcom,sm6125-dsi-phy-14nm

      - qcom,sm6150-dsi-phy-14nm



  reg:

    items:

Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml

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@@ -168,7 +168,8 @@ examples: 
            reg = <0xaf54000 0x104>,

                  <0xaf54200 0x0c0>,

                  <0xaf55000 0x770>,

                  <0xaf56000 0x09c>;

                  <0xaf56000 0x09c>,

                  <0xaf57000 0x09c>;



            interrupt-parent = <&mdss0>;

            interrupts = <12>;

Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml

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+108 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM6150 Display DPU



maintainers:

  - Abhinav Kumar <quic_abhinavk@quicinc.com>

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sm6150-dpu



  reg:

    items:

      - description: Address offset and size for mdp register set

      - description: Address offset and size for vbif register set



  reg-names:

    items:

      - const: mdp

      - const: vbif



  clocks:

    items:

      - description: Display ahb clock

      - description: Display hf axi clock

      - description: Display core clock

      - description: Display vsync clock



  clock-names:

    items:

      - const: iface

      - const: bus

      - const: core

      - const: vsync



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-controller@ae01000 {

        compatible = "qcom,sm6150-dpu";

        reg = <0x0ae01000 0x8f000>,

              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";



        clocks = <&dispcc_mdss_ahb_clk>,

                 <&gcc_disp_hf_axi_clk>,

                 <&dispcc_mdss_mdp_clk>,

                 <&dispcc_mdss_vsync_clk>;

        clock-names = "iface", "bus", "core", "vsync";



        assigned-clocks = <&dispcc_mdss_vsync_clk>;

        assigned-clock-rates = <19200000>;



        operating-points-v2 = <&mdp_opp_table>;

        power-domains = <&rpmhpd RPMHPD_CX>;



        interrupt-parent = <&mdss>;

        interrupts = <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dpu_intf0_out: endpoint {

                };

            };



            port@1 {

                reg = <1>;

                dpu_intf1_out: endpoint {

                  remote-endpoint = <&mdss_dsi0_in>;

                };

            };

        };



        mdp_opp_table: opp-table {

            compatible = "operating-points-v2";



            opp-19200000 {

              opp-hz = /bits/ 64 <19200000>;

              required-opps = <&rpmhpd_opp_low_svs>;

            };



            opp-25600000 {

              opp-hz = /bits/ 64 <25600000>;

              required-opps = <&rpmhpd_opp_svs>;

            };



            opp-307200000 {

              opp-hz = /bits/ 64 <307200000>;

              required-opps = <&rpmhpd_opp_nom>;

            };

        };

    };

...