Commit 24d1cdac authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/tc: Cache the pin assignment value 



Cache the pin assignment value. This is more consistent with the way the
max lane count value is tracked and a bit more efficient than reading
out the same value from HW each time it's queried.

Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250805073700.642107-19-imre.deak@intel.com


Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
parent cca7c083

drivers/gpu/drm/i915/display/intel_tc.c

+3 −1
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ struct intel_tc_port { 
	enum tc_port_mode mode;

	enum tc_port_mode init_mode;

	enum phy_fia phy_fia;

	enum intel_tc_pin_assignment pin_assignment;

	u8 phy_fia_idx;

	u8 max_lane_count;

};
@@ -382,6 +383,7 @@ static int get_max_lane_count(struct intel_tc_port *tc) 


static void read_pin_configuration(struct intel_tc_port *tc)

{

	tc->pin_assignment = get_pin_assignment(tc);

	tc->max_lane_count = get_max_lane_count(tc);

}
@@ -403,7 +405,7 @@ intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port) 
	if (!intel_encoder_is_tc(&dig_port->base))

		return INTEL_TC_PIN_ASSIGNMENT_NONE;



	return get_pin_assignment(tc);

	return tc->pin_assignment;

}



void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,