Commit 24f96d90 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/dsc: Add Selective Update register definitions 



Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.

Bspec: 71709
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
parent 681e1244

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

+12 −0
Original line number Diff line number Diff line
@@ -196,6 +196,18 @@ 
#define   DSC_PPS18_NSL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)

#define   DSC_PPS18_SL_OFFSET_ADJ(offset)	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)



#define _LNL_DSC0_SU_PARAMETER_SET_0_PA		0x78064

#define _LNL_DSC1_SU_PARAMETER_SET_0_PA		0x78164

#define _LNL_DSC0_SU_PARAMETER_SET_0_PB		0x78264

#define _LNL_DSC1_SU_PARAMETER_SET_0_PB		0x78364

#define LNL_DSC0_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB)

#define LNL_DSC1_SU_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB)



#define   DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK		REG_GENMASK(31, 20)

#define   DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))

#define   DSC_SUPS0_SU_PIC_HEIGHT_MASK			REG_GENMASK(15, 0)

#define   DSC_SUPS0_SU_PIC_HEIGHT(h)			REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h))



/* Icelake Rate Control Buffer Threshold Registers */

#define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)

#define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)