Commit 25375779 authored by Peter Wang's avatar Peter Wang Committed by Martin K. Petersen
Browse files

scsi: ufs: core: Change MCQ interrupt enable flow 



Move the MCQ interrupt enable process to
ufshcd_mcq_make_queues_operational() to ensure that interrupts are set
correctly when making queues operational, similar to
ufshcd_make_hba_operational(). This change addresses the issue where
ufshcd_mcq_make_queues_operational() was not fully operational due to
missing interrupt enablement.

This change only affects host drivers that call
ufshcd_mcq_make_queues_operational(), i.e. ufs-mediatek.

Signed-off-by: default avatarPeter Wang <peter.wang@mediatek.com>
Reviewed-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 0ac3c901

drivers/ufs/core/ufs-mcq.c

+11 −0
Original line number Diff line number Diff line
@@ -29,6 +29,10 @@ 
#define MCQ_ENTRY_SIZE_IN_DWORD	8

#define CQE_UCD_BA GENMASK_ULL(63, 7)



#define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\

				 UFSHCD_ERROR_MASK |\

				 MCQ_CQ_EVENT_STATUS)



/* Max mcq register polling time in microseconds */

#define MCQ_POLL_US 500000
@@ -355,9 +359,16 @@ EXPORT_SYMBOL_GPL(ufshcd_mcq_poll_cqe_lock); 
void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba)

{

	struct ufs_hw_queue *hwq;

	u32 intrs;

	u16 qsize;

	int i;



	/* Enable required interrupts */

	intrs = UFSHCD_ENABLE_MCQ_INTRS;

	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)

		intrs &= ~MCQ_CQ_EVENT_STATUS;

	ufshcd_enable_intr(hba, intrs);



	for (i = 0; i < hba->nr_hw_queues; i++) {

		hwq = &hba->uhq[i];

		hwq->id = i;

drivers/ufs/core/ufshcd.c

+1 −11
Original line number Diff line number Diff line
@@ -45,11 +45,6 @@ 
				 UTP_TASK_REQ_COMPL |\

				 UFSHCD_ERROR_MASK)



#define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\

				 UFSHCD_ERROR_MASK |\

				 MCQ_CQ_EVENT_STATUS)





/* UIC command timeout, unit: ms */

enum {

	UIC_CMD_TIMEOUT_DEFAULT	= 500,
@@ -372,7 +367,7 @@ EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 
 * @hba: per adapter instance

 * @intrs: interrupt bits

 */

static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)

void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)

{

	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);

	u32 new_val = old_val | intrs;
@@ -8909,16 +8904,11 @@ static int ufshcd_alloc_mcq(struct ufs_hba *hba) 
static void ufshcd_config_mcq(struct ufs_hba *hba)

{

	int ret;

	u32 intrs;



	ret = ufshcd_mcq_vops_config_esi(hba);

	hba->mcq_esi_enabled = !ret;

	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");



	intrs = UFSHCD_ENABLE_MCQ_INTRS;

	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)

		intrs &= ~MCQ_CQ_EVENT_STATUS;

	ufshcd_enable_intr(hba, intrs);

	ufshcd_mcq_make_queues_operational(hba);

	ufshcd_mcq_config_mac(hba, hba->nutrs);

include/ufs/ufshcd.h

+1 −0
Original line number Diff line number Diff line
@@ -1292,6 +1292,7 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 


void ufshcd_enable_irq(struct ufs_hba *hba);

void ufshcd_disable_irq(struct ufs_hba *hba);

void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs);

int ufshcd_alloc_host(struct device *, struct ufs_hba **);

int ufshcd_hba_enable(struct ufs_hba *hba);

int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);