Commit 2581f22f authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amd/pm: add pp_dpm_dcefclk for smu 14.0.2/3 



add pp_dpm_dcefclk for smu 14.0.2/3

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarJack Gui <Jack.Gui@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c14d5b50

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

+24 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] = { 
	CLK_MAP(MCLK,		PPCLK_UCLK),

	CLK_MAP(VCLK,		PPCLK_VCLK_0),

	CLK_MAP(DCLK,		PPCLK_DCLK_0),

	CLK_MAP(DCEFCLK,	PPCLK_DCFCLK),

};



static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -676,6 +677,22 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) 
		pcie_table->num_of_link_levels++;

	}



	/* dcefclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.dcef_table;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {

		ret = smu_v14_0_set_single_dpm_table(smu,

						     SMU_DCEFCLK,

						     dpm_table);

		if (ret)

			return ret;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	return 0;

}
@@ -1000,6 +1017,9 @@ static int smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context *smu, 
	case PPCLK_DCLK_0:

		member_type = METRICS_AVERAGE_DCLK;

		break;

	case PPCLK_DCFCLK:

		member_type = METRICS_CURR_DCEFCLK;

		break;

	default:

		return -EINVAL;

	}
@@ -1047,6 +1067,9 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, 
	case SMU_DCLK1:

		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);

		break;

	case SMU_DCEFCLK:

		single_dpm_table = &(dpm_context->dpm_tables.dcef_table);

		break;

	default:

		break;

	}
@@ -1060,6 +1083,7 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, 
	case SMU_VCLK1:

	case SMU_DCLK:

	case SMU_DCLK1:

	case SMU_DCEFCLK:

		ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);

		if (ret) {

			dev_err(smu->adev->dev, "Failed to get current clock freq!");