Commit 258b080d authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: fix SSPP_UBWC_STATIC_CTRL programming on UBWC 5.x+ 



Code in dpu_hw_sspp_setup_format() doesn't handle UBWC versions bigger
than 4.0. Replace switch-case with if-else checks, making sure that the
register is initialized on UBWC 5.x (and later) hosts.

Fixes: c2577fc1 ("drm/msm/dpu: Add support for SM8750")
Tested-by: Val Packett <val@packett.cool> # x1e80100-dell-latitude-7455
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/699280/
Link: https://lore.kernel.org/r/20260119-msm-ubwc-fixes-v4-4-0987acc0427f@oss.qualcomm.com
parent 5dcec3fc

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

+24 −21
Original line number Diff line number Diff line
@@ -284,6 +284,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, 


	if (fmt->fetch_mode != MDP_FETCH_LINEAR) {

		u32 hbb = ctx->ubwc->highest_bank_bit - 13;

		u32 ctrl_val;



		if (MSM_FORMAT_IS_UBWC(fmt))

			opmode |= MDSS_MDP_OP_BWC_EN;
@@ -291,30 +292,32 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, 
		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,

			DPU_FETCH_CONFIG_RESET_VALUE |

			hbb << 18);

		switch (ctx->ubwc->ubwc_enc_version) {

		case UBWC_1_0:



		if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, ubwc_ctrl_off,

					fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |

					BIT(8) |

					(hbb << 4));

			break;

		case UBWC_2_0:

			ctrl_val = fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |

				BIT(8) | (hbb << 4);

		} else if (ctx->ubwc->ubwc_enc_version == UBWC_2_0) {

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, ubwc_ctrl_off,

					fast_clear | (ctx->ubwc->ubwc_swizzle) |

					(hbb << 4));

			break;

		case UBWC_3_0:

			DPU_REG_WRITE(c, ubwc_ctrl_off,

					BIT(30) | (ctx->ubwc->ubwc_swizzle) |

					(hbb << 4));

			break;

		case UBWC_4_0:

			DPU_REG_WRITE(c, ubwc_ctrl_off,

					MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));

			break;

			ctrl_val = fast_clear | ctx->ubwc->ubwc_swizzle | (hbb << 4);

		} else if (ctx->ubwc->ubwc_enc_version == UBWC_3_0) {

			ctrl_val = BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb << 4);

		} else if (ctx->ubwc->ubwc_enc_version == UBWC_4_0) {

			ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);

		} else if (ctx->ubwc->ubwc_enc_version <= UBWC_6_0) {

			if (MSM_FORMAT_IS_YUV(fmt))

				ctrl_val = 0;

			else if (MSM_FORMAT_IS_DX(fmt)) /* or FP16, but it's unsupported */

				ctrl_val = BIT(30);

			else

				ctrl_val = BIT(30) | BIT(31);

			/* SDE also sets bits for lossy formats, but we don't support them yet */

		} else {

			DRM_WARN_ONCE("Unsupported UBWC version %x\n", ctx->ubwc->ubwc_enc_version);

			ctrl_val = 0;

		}



		DPU_REG_WRITE(c, ubwc_ctrl_off, ctrl_val);

	}



	opmode |= MDSS_MDP_OP_PE_OVERRIDE;