Commit 25b113f1 authored by Marek Vasut's avatar Marek Vasut Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rz-smarc-cru-csi-ov5645: Fix missing cells and reg in CSI2 subnode 



Add missing cells and reg DT property in the CSI2 subnode to fix the
following DTC W=1 warning:

    arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi:49.10-55.5: Warning (unit_address_vs_reg): /fragment@2/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property

Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://patch.msgid.link/20260326042411.215241-4-marek.vasut+renesas@mailbox.org


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 2016dde0

arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -46,7 +46,12 @@ &csi2 { 
	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;



			csi2_in: endpoint {

				clock-lanes = <0>;

				data-lanes = <1 2>;