Commit 25b47635 authored by Jacky Bai's avatar Jacky Bai Committed by Abel Vesa
Browse files

clk: imx: Add some delay before deassert the reset 



Some of the PCCs on i.MX8ULP have a sw_rst bit to control the peripheral
reset through SW method. For peripherals like GPU that need sync reset,
some delay is necessary befere & after release the reset to make sure the
HW is reset into a known status. So add some delay before & after release
reset.

Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20250801072153.1974428-1-ping.bai@nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 3a866087

drivers/clk/imx/clk-composite-7ulp.c

+13 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <linux/bits.h>

#include <linux/clk-provider.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/slab.h>
@@ -36,6 +37,9 @@ static int pcc_gate_enable(struct clk_hw *hw) 
	if (ret)

		return ret;



	/* Make sure the IP's clock is ready before release reset */

	udelay(1);



	spin_lock_irqsave(gate->lock, flags);

	/*

	 * release the sw reset for peripherals associated with
@@ -47,6 +51,15 @@ static int pcc_gate_enable(struct clk_hw *hw) 


	spin_unlock_irqrestore(gate->lock, flags);



	/*

	 * Read back the register to make sure the previous write has been

	 * done in the target HW register. For IP like GPU, after deassert

	 * the reset, need to wait for a while to make sure the sync reset

	 * is done

	 */

	readl(gate->reg);

	udelay(1);



	return 0;

}