Commit 25c1e741 authored by YiPeng Chai's avatar YiPeng Chai Committed by Alex Deucher
Browse files

drm/amd/ras: Update function and remove redundant code 



Update function and remove redundant code:
1. Update function to prepare for internal use.
2. Remove unused function code previously prepared
   for ioctl.

V2:
  Update commit message content.

Signed-off-by: default avatarYiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4c74635a

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c

+16 −94
Original line number Diff line number Diff line
@@ -36,67 +36,6 @@ 
#define AMDGPU_RAS_TYPE_AMDGPU   0x2

#define AMDGPU_RAS_TYPE_VF       0x3



static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core,

			struct ras_cmd_ctx *cmd)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;

	struct ras_query_interface_info_rsp *output_data =

		(struct ras_query_interface_info_rsp *)cmd->output_buff_raw;

	int ret;



	if (cmd->input_size != sizeof(struct ras_query_interface_info_req))

		return RAS_CMD__ERROR_INVALID_INPUT_SIZE;



	ret = ras_cmd_query_interface_info(ras_core, output_data);

	if (!ret) {

		output_data->plat_major_ver = 0;

		output_data->plat_minor_ver = 0;



		output_data->interface_type = amdgpu_sriov_vf(adev) ?

			RAS_CMD_INTERFACE_TYPE_VF : RAS_CMD_INTERFACE_TYPE_AMDGPU;



		cmd->output_size = sizeof(struct ras_query_interface_info_rsp);

	}



	return ret;

}



static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle)

{

	struct ras_core_context *ras_core;



	if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC))

		return NULL;



	ras_core = (struct ras_core_context *)(uintptr_t)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC);



	if (ras_cmd_get_dev_handle(ras_core) == dev_handle)

		return ras_core;



	return NULL;

}



static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core,

			struct ras_cmd_ctx *cmd)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;

	struct ras_cmd_devices_info_rsp *output_data =

			(struct ras_cmd_devices_info_rsp *)cmd->output_buff_raw;

	struct ras_cmd_dev_info *dev_info;



	dev_info = &output_data->devs[0];

	dev_info->dev_handle = ras_cmd_get_dev_handle(ras_core);

	dev_info->oam_id = adev->smuio.funcs->get_socket_id(adev);

	dev_info->ecc_enabled = 1;

	dev_info->ecc_supported = 1;



	output_data->dev_num = 1;

	output_data->version = 0;

	cmd->output_size = sizeof(struct ras_cmd_devices_info_rsp);



	return 0;

}



static int amdgpu_ras_trigger_error_prepare(struct ras_core_context *ras_core,

			struct ras_cmd_inject_error_req *block_info)

{
@@ -311,51 +250,34 @@ int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx 
	return res;

}



int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,

			uint8_t *cmd_buf, uint32_t buf_size)

int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd)

{

	struct ras_cmd_ctx *cmd = (struct ras_cmd_ctx *)cmd_buf;

	struct ras_core_context *cmd_core = NULL;

	struct ras_cmd_dev_handle *cmd_handle = NULL;

	struct ras_core_context *cmd_core = ras_core;

	int timeout = 60;

	int res;



	cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD;

	cmd->output_size = 0;



	if (!ras_core_is_enabled(ras_core))

	if (!ras_core_is_enabled(cmd_core))

		return RAS_CMD__ERROR_ACCESS_DENIED;



	if (cmd->cmd_id == RAS_CMD__QUERY_INTERFACE_INFO) {

		cmd->cmd_res = amdgpu_ras_query_interface_info(ras_core, cmd);

	} else if (cmd->cmd_id == RAS_CMD__GET_DEVICES_INFO) {

		cmd->cmd_res = amdgpu_ras_get_devices_info(ras_core, cmd);

	} else {

		cmd_handle = (struct ras_cmd_dev_handle *)cmd->input_buff_raw;

		cmd_core = ras_cmd_get_ras_core(cmd_handle->dev_handle);

		if (!cmd_core)

			return RAS_CMD__ERROR_INVALID_INPUT_DATA;



	while (ras_core_gpu_in_reset(cmd_core)) {

		msleep(1000);

		if (!timeout--)

			return RAS_CMD__ERROR_TIMEOUT;

	}





		if (!ras_core_is_enabled(cmd_core))

			return RAS_CMD__ERROR_ACCESS_DENIED;



	res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL);

	if (res == RAS_CMD__ERROR_UKNOWN_CMD)

		res = rascore_handle_cmd(cmd_core, cmd, NULL);



	cmd->cmd_res = res;

	}



	if ((cmd->cmd_res == RAS_CMD__SUCCESS) &&

	    ((cmd->output_size + sizeof(*cmd)) > buf_size)) {

		RAS_INFO("Insufficient command buffer size 0x%x!\n", buf_size);

	if (cmd->output_size > cmd->output_buf_size) {

		RAS_DEV_ERR(cmd_core->dev,

			"Output size 0x%x exceeds output buffer size 0x%x!\n",

			cmd->output_size, cmd->output_buf_size);

		return RAS_CMD__SUCCESS_EXEED_BUFFER;

	}

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h

+1 −2
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ struct ras_cmd_translate_memory_fd_rsp { 


int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core,

		struct ras_cmd_ctx *cmd, void *data);

int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,

			uint8_t *cmd_buf, uint32_t buf_size);

int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd);



#endif

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

+31 −0
Original line number Diff line number Diff line
@@ -578,3 +578,34 @@ bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev) 


	return ras_core_gpu_is_rma(ras_mgr->ras_core);

}



int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev,

			uint32_t cmd_id, void *input, uint32_t input_size,

			void *output, uint32_t out_size)

{

	struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);

	struct ras_cmd_ctx *cmd_ctx;

	uint32_t ctx_buf_size = PAGE_SIZE;

	int ret;



	if (!amdgpu_ras_mgr_is_ready(adev))

		return -EPERM;



	cmd_ctx = kzalloc(ctx_buf_size, GFP_KERNEL);

	if (!cmd_ctx)

		return -ENOMEM;



	cmd_ctx->cmd_id = cmd_id;



	memcpy(cmd_ctx->input_buff_raw, input, input_size);

	cmd_ctx->input_size = input_size;

	cmd_ctx->output_buf_size = ctx_buf_size - sizeof(*cmd_ctx);



	ret = amdgpu_ras_submit_cmd(ras_mgr->ras_core, cmd_ctx);

	if (!ret && !cmd_ctx->cmd_res && output && (out_size == cmd_ctx->output_size))

		memcpy(output, cmd_ctx->output_buff_raw, cmd_ctx->output_size);



	kfree(cmd_ctx);



	return ret;

}

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

+3 −0
Original line number Diff line number Diff line
@@ -72,4 +72,7 @@ int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, uint32_t *nps_m 
bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev,

			uint64_t addr);

bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev);

int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev,

		uint32_t cmd_id, void *input, uint32_t input_size,

		void *output, uint32_t out_size);

#endif

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

+2 −1
Original line number Diff line number Diff line
@@ -153,7 +153,8 @@ struct ras_cmd_ctx { 
	uint32_t cmd_res;

	uint32_t input_size;

	uint32_t output_size;

	uint32_t reserved[6];

	uint32_t output_buf_size;

	uint32_t reserved[5];

	uint8_t  input_buff_raw[RAS_CMD_MAX_IN_SIZE];

	uint8_t  output_buff_raw[];

};