Commit 25d51ebf authored by Subbaraya Sundeep's avatar Subbaraya Sundeep Committed by Jakub Kicinski
Browse files

octeontx2: Set appropriate PF, VF masks and shifts based on silicon 



Number of RVU PFs on CN20K silicon have increased to 96 from maximum
of 32 that were supported on earlier silicons. Every RVU PF and VF is
identified by HW using a 16bit PF_FUNC value. Due to the change in
Max number of PFs in CN20K, the bit encoding of this PF_FUNC has changed.

This patch handles the change by using helper functions(using silicon
check) to use PF,VF masks and shifts to support both new silicon CN20K,
OcteonTx series. These helper functions are used in different modules.

Also moved the NIX AF register offset macros to other files which
will be posted in coming patches.

Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: default avatarSai Krishna <saikrishnag@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Link: https://patch.msgid.link/1749639716-13868-2-git-send-email-sbhatta@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent b34441e3

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+2 −3
Original line number Diff line number Diff line
@@ -18,9 +18,8 @@ 
#define OTX2_CPT_MAX_VFS_NUM 128

#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \

		(((blk) << 20) | ((slot) << 12) | (offs))

#define OTX2_CPT_RVU_PFFUNC(pf, func)	\

		((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \

		(((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))



#define OTX2_CPT_RVU_PFFUNC(pdev, pf, func) rvu_make_pcifunc(pdev, pf, func)



#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF

#define OTX2_CPT_NAME_LENGTH 64

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

+6 −7
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ static int send_inline_ipsec_inbound_msg(struct otx2_cptpf_dev *cptpf, 
	memset(req, 0, sizeof(*req));

	req->hdr.id = MBOX_MSG_CPT_INLINE_IPSEC_CFG;

	req->hdr.sig = OTX2_MBOX_REQ_SIG;

	req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0);

	req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptpf->pdev, cptpf->pf_id, 0);

	req->dir = CPT_INLINE_INBOUND;

	req->slot = slot;

	req->sso_pf_func_ovrd = cptpf->sso_pf_func_ovrd;
@@ -184,7 +184,8 @@ static int rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, u8 egrp, 
		nix_req->gen_cfg.opcode = cpt_inline_rx_opcode(pdev);

	nix_req->gen_cfg.param1 = req->param1;

	nix_req->gen_cfg.param2 = req->param2;

	nix_req->inst_qsel.cpt_pf_func = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0);

	nix_req->inst_qsel.cpt_pf_func =

		OTX2_CPT_RVU_PFFUNC(cptpf->pdev, cptpf->pf_id, 0);

	nix_req->inst_qsel.cpt_slot = 0;

	ret = otx2_cpt_send_mbox_msg(&cptpf->afpf_mbox, pdev);

	if (ret)
@@ -392,9 +393,8 @@ void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work) 
		msg = (struct mbox_msghdr *)(mdev->mbase + offset);



		/* Set which VF sent this message based on mbox IRQ */

		msg->pcifunc = ((u16)cptpf->pf_id << RVU_PFVF_PF_SHIFT) |

				((vf->vf_id + 1) & RVU_PFVF_FUNC_MASK);



		msg->pcifunc = rvu_make_pcifunc(cptpf->pdev, cptpf->pf_id,

						(vf->vf_id + 1));

		err = cptpf_handle_vf_req(cptpf, vf, msg,

					  msg->next_msgoff - offset);

		/*
@@ -469,8 +469,7 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf, 


	switch (msg->id) {

	case MBOX_MSG_READY:

		cptpf->pf_id = (msg->pcifunc >> RVU_PFVF_PF_SHIFT) &

				RVU_PFVF_PF_MASK;

		cptpf->pf_id = rvu_get_pf(cptpf->pdev, msg->pcifunc);

		break;

	case MBOX_MSG_MSIX_OFFSET:

		rsp_msix = (struct msix_offset_rsp *) msg;

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

+3 −1
Original line number Diff line number Diff line
@@ -176,7 +176,9 @@ static int cptx_set_ucode_base(struct otx2_cpt_eng_grp_info *eng_grp, 
	/* Set PF number for microcode fetches */

	ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

				    CPT_AF_PF_FUNC,

				    cptpf->pf_id << RVU_PFVF_PF_SHIFT, blkaddr);

				    rvu_make_pcifunc(cptpf->pdev,

						     cptpf->pf_id, 0),

				    blkaddr);

	if (ret)

		return ret;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

+3 −3
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type) 
	}

	req->hdr.id = MBOX_MSG_GET_ENG_GRP_NUM;

	req->hdr.sig = OTX2_MBOX_REQ_SIG;

	req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);

	req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->pdev, cptvf->vf_id, 0);

	req->eng_type = eng_type;



	return otx2_cpt_send_mbox_msg(mbox, pdev);
@@ -210,7 +210,7 @@ int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf) 
	}

	req->id = MBOX_MSG_GET_KVF_LIMITS;

	req->sig = OTX2_MBOX_REQ_SIG;

	req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);

	req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->pdev, cptvf->vf_id, 0);



	return otx2_cpt_send_mbox_msg(mbox, pdev);

}
@@ -230,7 +230,7 @@ int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf) 
	}

	req->id = MBOX_MSG_GET_CAPS;

	req->sig = OTX2_MBOX_REQ_SIG;

	req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0);

	req->pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->pdev, cptvf->vf_id, 0);



	return otx2_cpt_send_mbox_msg(mbox, pdev);

}

drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c

+3 −3
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ int mcs_add_intr_wq_entry(struct mcs *mcs, struct mcs_intr_event *event) 
	if (pcifunc & RVU_PFVF_FUNC_MASK)

		pfvf = &mcs->vf[rvu_get_hwvf(rvu, pcifunc)];

	else

		pfvf = &mcs->pf[rvu_get_pf(pcifunc)];

		pfvf = &mcs->pf[rvu_get_pf(rvu->pdev, pcifunc)];



	event->intr_mask &= pfvf->intr_mask;
@@ -123,7 +123,7 @@ static int mcs_notify_pfvf(struct mcs_intr_event *event, struct rvu *rvu) 
	struct mcs_intr_info *req;

	int pf;



	pf = rvu_get_pf(event->pcifunc);

	pf = rvu_get_pf(rvu->pdev, event->pcifunc);



	mutex_lock(&rvu->mbox_lock);
@@ -193,7 +193,7 @@ int rvu_mbox_handler_mcs_intr_cfg(struct rvu *rvu, 
	if (pcifunc & RVU_PFVF_FUNC_MASK)

		pfvf = &mcs->vf[rvu_get_hwvf(rvu, pcifunc)];

	else

		pfvf = &mcs->pf[rvu_get_pf(pcifunc)];

		pfvf = &mcs->pf[rvu_get_pf(rvu->pdev, pcifunc)];



	mcs->pf_map[0] = pcifunc;

	pfvf->intr_mask = req->intr_mask;