media: intel/ipu6: add Intel IPU6 PCI device driver

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (C) 2018 - 2024 Intel Corporation */

#ifndef IPU6_PLATFORM_REGS_H

#define IPU6_PLATFORM_REGS_H

#include <linux/bits.h>

/*

 * IPU6 uses uniform address within IPU6, therefore all subsystem registers

 * locates in one single space starts from 0 but in different sctions with

 * different addresses, the subsystem offsets are defined to 0 as the

 * register definition will have the address offset to 0.

 */

#define IPU6_UNIFIED_OFFSET			0

#define IPU6_ISYS_IOMMU0_OFFSET		0x2e0000

#define IPU6_ISYS_IOMMU1_OFFSET		0x2e0500

#define IPU6_ISYS_IOMMUI_OFFSET		0x2e0a00

#define IPU6_PSYS_IOMMU0_OFFSET		0x1b0000

#define IPU6_PSYS_IOMMU1_OFFSET		0x1b0700

#define IPU6_PSYS_IOMMU1R_OFFSET	0x1b0e00

#define IPU6_PSYS_IOMMUI_OFFSET		0x1b1500

/* the offset from IOMMU base register */

#define IPU6_MMU_L1_STREAM_ID_REG_OFFSET	0x0c

#define IPU6_MMU_L2_STREAM_ID_REG_OFFSET	0x4c

#define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET	0x8c

#define IPU6_MMU_INFO_OFFSET		0x8

#define IPU6_ISYS_SPC_OFFSET		0x210000

#define IPU6SE_PSYS_SPC_OFFSET		0x110000

#define IPU6_PSYS_SPC_OFFSET		0x118000

#define IPU6_ISYS_DMEM_OFFSET		0x200000

#define IPU6_PSYS_DMEM_OFFSET		0x100000

#define IPU6_REG_ISYS_UNISPART_IRQ_EDGE			0x27c000

#define IPU6_REG_ISYS_UNISPART_IRQ_MASK			0x27c004

#define IPU6_REG_ISYS_UNISPART_IRQ_STATUS		0x27c008

#define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR		0x27c00c

#define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE		0x27c010

#define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE	0x27c014

#define IPU6_REG_ISYS_UNISPART_SW_IRQ_REG		0x27c414

#define IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG		0x27c418

#define IPU6_ISYS_UNISPART_IRQ_CSI0			BIT(2)

#define IPU6_ISYS_UNISPART_IRQ_CSI1			BIT(3)

#define IPU6_ISYS_UNISPART_IRQ_SW			BIT(22)

#define IPU6_REG_ISYS_ISL_TOP_IRQ_EDGE			0x2b0200

#define IPU6_REG_ISYS_ISL_TOP_IRQ_MASK			0x2b0204

#define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS		0x2b0208

#define IPU6_REG_ISYS_ISL_TOP_IRQ_CLEAR			0x2b020c

#define IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE		0x2b0210

#define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE	0x2b0214

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE			0x2d2100

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK			0x2d2104

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_STATUS		0x2d2108

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_CLEAR		0x2d210c

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_ENABLE		0x2d2110

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_LEVEL_NOT_PULSE	0x2d2114

/* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */

#define IPU6_REG_ISYS_CDC_THRESHOLD(i)		(0x27c400 + ((i) * 4))

#define IPU6_CSI_IRQ_NUM_PER_PIPE			4

#define IPU6SE_ISYS_CSI_PORT_NUM			4

#define IPU6_ISYS_CSI_PORT_NUM				8

#define IPU6_ISYS_CSI_PORT_IRQ(irq_num)		BIT(irq_num)

/* PKG DIR OFFSET in IMR in secure mode */

#define IPU6_PKG_DIR_IMR_OFFSET			0x40

#define IPU6_ISYS_REG_SPC_STATUS_CTRL		0x0

#define IPU6_ISYS_SPC_STATUS_START			BIT(1)

#define IPU6_ISYS_SPC_STATUS_RUN			BIT(3)

#define IPU6_ISYS_SPC_STATUS_READY			BIT(5)

#define IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE	BIT(12)

#define IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH		BIT(13)

#define IPU6_PSYS_REG_SPC_STATUS_CTRL			0x0

#define IPU6_PSYS_REG_SPC_START_PC			0x4

#define IPU6_PSYS_REG_SPC_ICACHE_BASE			0x10

#define IPU6_REG_PSYS_INFO_SEG_0_CONFIG_ICACHE_MASTER	0x14

#define IPU6_PSYS_SPC_STATUS_START			BIT(1)

#define IPU6_PSYS_SPC_STATUS_RUN			BIT(3)

#define IPU6_PSYS_SPC_STATUS_READY			BIT(5)

#define IPU6_PSYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE	BIT(12)

#define IPU6_PSYS_SPC_STATUS_ICACHE_PREFETCH		BIT(13)

#define IPU6_PSYS_REG_SPP0_STATUS_CTRL			0x20000

#define IPU6_INFO_ENABLE_SNOOP			BIT(0)

#define IPU6_INFO_DEC_FORCE_FLUSH		BIT(1)

#define IPU6_INFO_DEC_PASS_THROUGH		BIT(2)

#define IPU6_INFO_ZLW				BIT(3)

#define IPU6_INFO_REQUEST_DESTINATION_IOSF	BIT(9)

#define IPU6_INFO_IMR_BASE			BIT(10)

#define IPU6_INFO_IMR_DESTINED			BIT(11)

#define IPU6_INFO_REQUEST_DESTINATION_PRIMARY IPU6_INFO_REQUEST_DESTINATION_IOSF

/*

 * s2m_pixel_soc_pixel_remapping is dedicated for the enabling of the

 * pixel s2m remp ability.Remap here  means that s2m rearange the order

 * of the pixels in each 4 pixels group.

 * For examle, mirroring remping means that if input's 4 first pixels

 * are 1 2 3 4 then in output we should see 4 3 2 1 in this 4 first pixels.

 * 0xE4 is from s2m MAS document. It means no remapping.

 */

#define S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4

/*

 * csi_be_soc_pixel_remapping is for the enabling of the pixel remapping.

 * This remapping is exactly like the stream2mmio remapping.

 */

#define CSI_BE_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING    0xe4

#define IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR		0x1ae000

#define IPU6_REG_DMA_TOP_AB_GROUP2_BASE_ADDR		0x1af000

#define IPU6_REG_DMA_TOP_AB_RING_MIN_OFFSET(n)		(0x4 + (n) * 0xc)

#define IPU6_REG_DMA_TOP_AB_RING_MAX_OFFSET(n)		(0x8 + (n) * 0xc)

#define IPU6_REG_DMA_TOP_AB_RING_ACCESS_OFFSET(n)	(0xc + (n) * 0xc)

enum ipu6_device_ab_group1_target_id {

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R0_SPC_DMEM,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R1_SPC_DMEM,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R2_SPC_DMEM,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R3_SPC_STATUS_REG,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R4_SPC_MASTER_BASE_ADDR,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R5_SPC_PC_STALL,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R6_SPC_EQ,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R7_SPC_RESERVED,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R8_SPC_RESERVED,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R9_SPP0,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R10_SPP1,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R11_CENTRAL_R1,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R12_IRQ,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R13_CENTRAL_R2,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R14_DMA,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R15_DMA,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R16_GP,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R17_ZLW_INSERTER,

	IPU6_DEVICE_AB_GROUP1_TARGET_ID_R18_AB,

};

enum nci_ab_access_mode {

	NCI_AB_ACCESS_MODE_RW,	/* read & write */

	NCI_AB_ACCESS_MODE_RO,	/* read only */

	NCI_AB_ACCESS_MODE_WO,	/* write only */

	NCI_AB_ACCESS_MODE_NA,	/* No access at all */

};

/* IRQ-related registers in PSYS */

#define IPU6_REG_PSYS_GPDEV_IRQ_EDGE		0x1aa200

#define IPU6_REG_PSYS_GPDEV_IRQ_MASK		0x1aa204

#define IPU6_REG_PSYS_GPDEV_IRQ_STATUS		0x1aa208

#define IPU6_REG_PSYS_GPDEV_IRQ_CLEAR		0x1aa20c

#define IPU6_REG_PSYS_GPDEV_IRQ_ENABLE		0x1aa210

#define IPU6_REG_PSYS_GPDEV_IRQ_LEVEL_NOT_PULSE	0x1aa214

/* There are 8 FW interrupts, n = 0..7 */

#define IPU6_PSYS_GPDEV_FWIRQ0			5

#define IPU6_PSYS_GPDEV_FWIRQ1			6

#define IPU6_PSYS_GPDEV_FWIRQ2			7

#define IPU6_PSYS_GPDEV_FWIRQ3			8

#define IPU6_PSYS_GPDEV_FWIRQ4			9

#define IPU6_PSYS_GPDEV_FWIRQ5			10

#define IPU6_PSYS_GPDEV_FWIRQ6			11

#define IPU6_PSYS_GPDEV_FWIRQ7			12

#define IPU6_PSYS_GPDEV_IRQ_FWIRQ(n)		BIT(n)

#define IPU6_REG_PSYS_GPDEV_FWIRQ(n)		(4 * (n) + 0x1aa100)

#endif /* IPU6_PLATFORM_REGS_H */

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (C) 2013 - 2024 Intel Corporation */

#ifndef IPU6_H

#define IPU6_H

#include <linux/list.h>

#include <linux/pci.h>

#include <linux/types.h>

#include "ipu6-buttress.h"

struct firmware;

struct pci_dev;

struct ipu6_bus_device;

#define IPU6_NAME			"intel-ipu6"

#define IPU6_MEDIA_DEV_MODEL_NAME	"ipu6"

#define IPU6SE_FIRMWARE_NAME		"intel/ipu/ipu6se_fw.bin"

#define IPU6EP_FIRMWARE_NAME		"intel/ipu/ipu6ep_fw.bin"

#define IPU6_FIRMWARE_NAME		"intel/ipu/ipu6_fw.bin"

#define IPU6EPMTL_FIRMWARE_NAME		"intel/ipu/ipu6epmtl_fw.bin"

#define IPU6EPADLN_FIRMWARE_NAME	"intel/ipu/ipu6epadln_fw.bin"

enum ipu6_version {

	IPU6_VER_INVALID = 0,

	IPU6_VER_6 = 1,

	IPU6_VER_6SE = 3,

	IPU6_VER_6EP = 5,

	IPU6_VER_6EP_MTL = 6,

};

/*

 * IPU6 - TGL

 * IPU6SE - JSL

 * IPU6EP - ADL/RPL

 * IPU6EP_MTL - MTL

 */

static inline bool is_ipu6se(u8 hw_ver)

{

	return hw_ver == IPU6_VER_6SE;

}

static inline bool is_ipu6ep(u8 hw_ver)

{

	return hw_ver == IPU6_VER_6EP;

}

static inline bool is_ipu6ep_mtl(u8 hw_ver)

{

	return hw_ver == IPU6_VER_6EP_MTL;

}

static inline bool is_ipu6_tgl(u8 hw_ver)

{

	return hw_ver == IPU6_VER_6;

}

/*

 * ISYS DMA can overshoot. For higher resolutions over allocation is one line

 * but it must be at minimum 1024 bytes. Value could be different in

 * different versions / generations thus provide it via platform data.

 */

#define IPU6_ISYS_OVERALLOC_MIN		1024

/* Physical pages in GDA is 128, page size is 2K for IPU6, 1K for others */

#define IPU6_DEVICE_GDA_NR_PAGES		128

/* Virtualization factor to calculate the available virtual pages */

#define IPU6_DEVICE_GDA_VIRT_FACTOR	32

struct ipu6_device {

	struct pci_dev *pdev;

	struct list_head devices;

	struct ipu6_bus_device *isys;

	struct ipu6_bus_device *psys;

	struct ipu6_buttress buttress;

	const struct firmware *cpd_fw;

	const char *cpd_fw_name;

	u32 cpd_metadata_cmpnt_size;

	void __iomem *base;

	bool need_ipc_reset;

	bool secure_mode;

	u8 hw_ver;

	bool bus_ready_to_probe;

};

#define IPU6_ISYS_NAME "isys"

#define IPU6_PSYS_NAME "psys"

#define IPU6_MMU_MAX_DEVICES		4

#define IPU6_MMU_ADDR_BITS		32

/* The firmware is accessible within the first 2 GiB only in non-secure mode. */

#define IPU6_MMU_ADDR_BITS_NON_SECURE	31

#define IPU6_MMU_MAX_TLB_L1_STREAMS	32

#define IPU6_MMU_MAX_TLB_L2_STREAMS	32

#define IPU6_MAX_LI_BLOCK_ADDR		128

#define IPU6_MAX_L2_BLOCK_ADDR		64

#define IPU6SE_ISYS_NUM_STREAMS          IPU6SE_NONSECURE_STREAM_ID_MAX

#define IPU6_ISYS_NUM_STREAMS            IPU6_NONSECURE_STREAM_ID_MAX

/*

 * To maximize the IOSF utlization, IPU6 need to send requests in bursts.

 * At the DMA interface with the buttress, there are CDC FIFOs with burst

 * collection capability. CDC FIFO burst collectors have a configurable

 * threshold and is configured based on the outcome of performance measurements.

 *

 * isys has 3 ports with IOSF interface for VC0, VC1 and VC2

 * psys has 4 ports with IOSF interface for VC0, VC1w, VC1r and VC2

 *

 * Threshold values are pre-defined and are arrived at after performance

 * evaluations on a type of IPU6

 */

#define IPU6_MAX_VC_IOSF_PORTS		4

/*

 * IPU6 must configure correct arbitration mechanism related to the IOSF VC

 * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on

 * stall and 1 means stall until the request is completed.

 */

#define IPU6_BTRS_ARB_MODE_TYPE_REARB	0

#define IPU6_BTRS_ARB_MODE_TYPE_STALL	1

/* Currently chosen arbitration mechanism for VC0 */

#define IPU6_BTRS_ARB_STALL_MODE_VC0	\

			IPU6_BTRS_ARB_MODE_TYPE_REARB

/* Currently chosen arbitration mechanism for VC1 */

#define IPU6_BTRS_ARB_STALL_MODE_VC1	\

			IPU6_BTRS_ARB_MODE_TYPE_REARB

/*

 * MMU Invalidation HW bug workaround by ZLW mechanism

 *

 * Old IPU6 MMUV2 has a bug in the invalidation mechanism which might result in

 * wrong translation or replication of the translation. This will cause data

 * corruption. So we cannot directly use the MMU V2 invalidation registers

 * to invalidate the MMU. Instead, whenever an invalidate is called, we need to

 * clear the TLB by evicting all the valid translations by filling it with trash

 * buffer (which is guaranteed not to be used by any other processes). ZLW is

 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW

 * or Zero length write, is pre-fetch mechanism to pre-fetch the pages in

 * advance to the L1 and L2 caches without triggering any memory operations.

 *

 * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream

 * One L1 block has 16 entries, hence points to 16 * 4K pages

 * L2 -> 16 streams and 32 blocks. 2 blocks per streams

 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range

 * 2 blocks per L2 stream means, 1 stream points to 8MB range

 *

 * As we need to clear the caches and 8MB being the biggest cache size, we need

 * to have trash buffer which points to 8MB address range. As these trash

 * buffers are not used for any memory transactions, we need only the least

 * amount of physical memory. So we reserve 8MB IOVA address range but only

 * one page is reserved from physical memory. Each of this 8MB IOVA address

 * range is then mapped to the same physical memory page.

 */

/* One L2 entry maps 1024 L1 entries and one L1 entry per page */

#define IPU6_MMUV2_L2_RANGE		(1024 * PAGE_SIZE)

/* Max L2 blocks per stream */

#define IPU6_MMUV2_MAX_L2_BLOCKS	2

/* Max L1 blocks per stream */

#define IPU6_MMUV2_MAX_L1_BLOCKS	16

#define IPU6_MMUV2_TRASH_RANGE	(IPU6_MMUV2_L2_RANGE * IPU6_MMUV2_MAX_L2_BLOCKS)

/* Entries per L1 block */

#define MMUV2_ENTRIES_PER_L1_BLOCK	16

#define MMUV2_TRASH_L1_BLOCK_OFFSET	(MMUV2_ENTRIES_PER_L1_BLOCK * PAGE_SIZE)

#define MMUV2_TRASH_L2_BLOCK_OFFSET	IPU6_MMUV2_L2_RANGE

/*

 * In some of the IPU6 MMUs, there is provision to configure L1 and L2 page

 * table caches. Both these L1 and L2 caches are divided into multiple sections

 * called streams. There is maximum 16 streams for both caches. Each of these

 * sections are subdivided into multiple blocks. When nr_l1streams = 0 and

 * nr_l2streams = 0, means the MMU is of type MMU_V1 and do not support

 * L1/L2 page table caches.

 *

 * L1 stream per block sizes are configurable and varies per usecase.

 * L2 has constant block sizes - 2 blocks per stream.

 *

 * MMU1 support pre-fetching of the pages to have less cache lookup misses. To

 * enable the pre-fetching, MMU1 AT (Address Translator) device registers

 * need to be configured.

 *

 * There are four types of memory accesses which requires ZLW configuration.

 * ZLW(Zero Length Write) is a mechanism to enable VT-d pre-fetching on IOMMU.

 *

 * 1. Sequential Access or 1D mode

 *	Set ZLW_EN -> 1

 *	set ZLW_PAGE_CROSS_1D -> 1

 *	Set ZLW_N to "N" pages so that ZLW will be inserte N pages ahead where

 *		  N is pre-defined and hardcoded in the platform data

 *	Set ZLW_2D -> 0

 *

 * 2. ZLW 2D mode

 *	Set ZLW_EN -> 1

 *	set ZLW_PAGE_CROSS_1D -> 1,

 *	Set ZLW_N -> 0

 *	Set ZLW_2D -> 1

 *

 * 3. ZLW Enable (no 1D or 2D mode)

 *	Set ZLW_EN -> 1

 *	set ZLW_PAGE_CROSS_1D -> 0,

 *	Set ZLW_N -> 0

 *	Set ZLW_2D -> 0

 *

 * 4. ZLW disable

 *	Set ZLW_EN -> 0

 *	set ZLW_PAGE_CROSS_1D -> 0,

 *	Set ZLW_N -> 0

 *	Set ZLW_2D -> 0

 *

 * To configure the ZLW for the above memory access, four registers are

 * available. Hence to track these four settings, we have the following entries

 * in the struct ipu6_mmu_hw. Each of these entries are per stream and

 * available only for the L1 streams.

 *

 * a. l1_zlw_en -> To track zlw enabled per stream (ZLW_EN)

 * b. l1_zlw_1d_mode -> Track 1D mode per stream. ZLW inserted at page boundary

 * c. l1_ins_zlw_ahead_pages -> to track how advance the ZLW need to be inserted

 *			Insert ZLW request N pages ahead address.

 * d. l1_zlw_2d_mode -> To track 2D mode per stream (ZLW_2D)

 *

 *

 * Currently L1/L2 streams, blocks, AT ZLW configurations etc. are pre-defined

 * as per the usecase specific calculations. Any change to this pre-defined

 * table has to happen in sync with IPU6 FW.

 */

struct ipu6_mmu_hw {

	union {

		unsigned long offset;

		void __iomem *base;

	};

	u32 info_bits;

	u8 nr_l1streams;

	/*

	 * L1 has variable blocks per stream - total of 64 blocks and maximum of

	 * 16 blocks per stream. Configurable by using the block start address

	 * per stream. Block start address is calculated from the block size

	 */

	u8 l1_block_sz[IPU6_MMU_MAX_TLB_L1_STREAMS];

	/* Is ZLW is enabled in each stream */

	bool l1_zlw_en[IPU6_MMU_MAX_TLB_L1_STREAMS];

	bool l1_zlw_1d_mode[IPU6_MMU_MAX_TLB_L1_STREAMS];

	u8 l1_ins_zlw_ahead_pages[IPU6_MMU_MAX_TLB_L1_STREAMS];

	bool l1_zlw_2d_mode[IPU6_MMU_MAX_TLB_L1_STREAMS];

	u32 l1_stream_id_reg_offset;

	u32 l2_stream_id_reg_offset;

	u8 nr_l2streams;

	/*

	 * L2 has fixed 2 blocks per stream. Block address is calculated

	 * from the block size

	 */

	u8 l2_block_sz[IPU6_MMU_MAX_TLB_L2_STREAMS];

	/* flag to track if WA is needed for successive invalidate HW bug */

	bool insert_read_before_invalidate;

};

struct ipu6_mmu_pdata {

	u32 nr_mmus;

	struct ipu6_mmu_hw mmu_hw[IPU6_MMU_MAX_DEVICES];

	int mmid;

};

struct ipu6_isys_csi2_pdata {

	void __iomem *base;

};

struct ipu6_isys_internal_csi2_pdata {

	u32 nports;

	u32 irq_mask;

	u32 ctrl0_irq_edge;

	u32 ctrl0_irq_clear;

	u32 ctrl0_irq_mask;

	u32 ctrl0_irq_enable;

	u32 ctrl0_irq_lnp;

	u32 ctrl0_irq_status;

	u32 fw_access_port_ofs;

};

struct ipu6_isys_internal_tpg_pdata {

	u32 ntpgs;

	u32 *offsets;

	u32 *sels;

};

struct ipu6_hw_variants {

	unsigned long offset;

	u32 nr_mmus;

	struct ipu6_mmu_hw mmu_hw[IPU6_MMU_MAX_DEVICES];

	u8 cdc_fifos;

	u8 cdc_fifo_threshold[IPU6_MAX_VC_IOSF_PORTS];

	u32 dmem_offset;

	u32 spc_offset;

};

struct ipu6_isys_internal_pdata {

	struct ipu6_isys_internal_csi2_pdata csi2;

	struct ipu6_hw_variants hw_variant;

	u32 num_parallel_streams;

	u32 isys_dma_overshoot;

	u32 sram_gran_shift;

	u32 sram_gran_size;

	u32 max_sram_size;

	u32 max_streams;

	u32 max_send_queues;

	u32 max_sram_blocks;

	u32 max_devq_size;

	u32 sensor_type_start;

	u32 sensor_type_end;

	u32 ltr;

	u32 memopen_threshold;

	bool enhanced_iwake;

};

struct ipu6_isys_pdata {

	void __iomem *base;

	const struct ipu6_isys_internal_pdata *ipdata;

};

struct ipu6_psys_internal_pdata {

	struct ipu6_hw_variants hw_variant;

};

struct ipu6_psys_pdata {

	void __iomem *base;

	const struct ipu6_psys_internal_pdata *ipdata;

};

int ipu6_fw_authenticate(void *data, u64 val);

void ipu6_configure_spc(struct ipu6_device *isp,

			const struct ipu6_hw_variants *hw_variant,

			int pkg_dir_idx, void __iomem *base, u64 *pkg_dir,

			dma_addr_t pkg_dir_dma_addr);

#endif /* IPU6_H */