Commit 2631c2b8 authored by Inochi Amaoto's avatar Inochi Amaoto Committed by Thomas Gleixner
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dt-bindings: interrupt-controller: Add T-HEAD C900 ACLINT SSWI device



Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully
featured T-HEAD ACLINT device. This ACLINT device contains a SSWI device to
support fast S-mode IPI.

Add necessary compatible string for the T-HEAD ACLINT SSWI device.

Signed-off-by: default avatarInochi Amaoto <inochiama@gmail.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/all/20241031060859.722258-2-inochiama@gmail.com
Link: https://www.xrvm.com/product/xuantie/C920
parent 194c4f56
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device

maintainers:
  - Inochi Amaoto <inochiama@outlook.com>

description:
  The SSWI device is a part of the THEAD ACLINT device. It provides
  supervisor-level IPI functionality for a set of HARTs on a THEAD
  platform. It provides a register to set an IPI (SETSSIP) for each
  HART connected to the SSWI device.

properties:
  compatible:
    items:
      - enum:
          - sophgo,sg2044-aclint-sswi
      - const: thead,c900-aclint-sswi

  reg:
    maxItems: 1

  "#interrupt-cells":
    const: 0

  interrupt-controller: true

  interrupts-extended:
    minItems: 1
    maxItems: 4095

additionalProperties: false

required:
  - compatible
  - reg
  - "#interrupt-cells"
  - interrupt-controller
  - interrupts-extended

examples:
  - |
    interrupt-controller@94000000 {
      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
      reg = <0x94000000 0x00004000>;
      #interrupt-cells = <0>;
      interrupt-controller;
      interrupts-extended = <&cpu1intc 1>,
                            <&cpu2intc 1>,
                            <&cpu3intc 1>,
                            <&cpu4intc 1>;
    };
...