Unverified Commit 264200cc authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Stephen Boyd
Browse files

clk: Fix typos



Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and
uses updated).

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 65df390b
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ static void ccu_div_clk_unregister(struct ccu_div_data *data, bool defer)
{
	int idx;

	/* Uninstall only the clocks registered on the specfied stage */
	/* Uninstall only the clocks registered on the specified stage */
	for (idx = 0; idx < data->divs_num; ++idx) {
		if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
			continue;
+1 −1
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ static void ccu_pll_clk_unregister(struct ccu_pll_data *data, bool defer)
{
	int idx;

	/* Uninstall only the clocks registered on the specfied stage */
	/* Uninstall only the clocks registered on the specified stage */
	for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
		if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
			continue;
+1 −1
Original line number Diff line number Diff line
@@ -1555,7 +1555,7 @@ static const char *const bcm2835_clock_osc_parents[] = {
	.parents = bcm2835_clock_osc_parents,				\
	__VA_ARGS__)

/* main peripherial parent mux */
/* main peripheral parent mux */
static const char *const bcm2835_clock_per_parents[] = {
	"gnd",
	"xosc",
+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static unsigned long bcm53573_ilp_recalc_rate(struct clk_hw *hw,
	/*
	 * At minimum we should loop for a bit to let hardware do the
	 * measurement. This isn't very accurate however, so for a better
	 * precision lets try getting 20 different values for and use average.
	 * precision let's try getting 20 different values and use average.
	 */
	while (num < 20) {
		regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &cur_val);
+1 −1
Original line number Diff line number Diff line
@@ -319,7 +319,7 @@ berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

	/*
	 * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide.
	 * AV2/AV3 form a fractional divider, where only specfic values for AV3
	 * AV2/AV3 form a fractional divider, where only specific values for AV3
	 * are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass.
	 */
	if (ch->index < 6) {
Loading